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2.4
TWI timing Requirement
Table 2-2. TWI timing Requirement
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
Digital Input Level High
VIH
0.8
VDD
Digital Input Level Low
VIL
0.2
VDD
CLK Frequency
FCLK
10
1,000
kHz
CLK High Time
t
CH
500
ns
CLK Low Time
t
CL
500
ns
CLK Delay Time
t
CD
CLK delay time for the first falling
edge of the TWI_RST command,
see Figure 2-6
20
15,000
ns
DATA Delay Time
t
DD
The data delay time from the last
CLK rising edge of the TWI
command to the time DATA return
to default status
15,000
ns
DATA Setup Time
t
DS
From DATA change to CLK falling
edge
20
ns
DATA Hold Time
t
DH
From CLK falling edge to DATA
change
200
ns
t
DS
t
DH
t
CH
t
CL
RFCLK
RFDAT
Figure 2-4. TWI Timing Diagram
RFCLK
RFDAT
W/R
A5
1
A4
A2
A1
A3
A0
D6
D5
D7
D4
D2
D1
D3
X
t
DD
Default
State
D0
Figure 2-5. TWI 16-bit Command Timing Diagram
A group of TWI commands are composed of 16-bit data sent by RFCLK and RFDAT. The above diagram is a
set of standard command timing format. In the high 8-bit data, the first bit is fixed to 1. Bit6 is a read/write
distinction bit, "0" represents the write operation. "1" represents the read operation. The latter 6-bit is the
register address of the operation. The low 8-bit data is the writing value or reading value of the operation
register.
