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DS861PP3

CS5346

7. REGISTER DESCRIPTION

7.1

Chip ID - Register 01h

Function:

This register is Read-Only. Bits 7 through 4 are the part number ID, which is 1100b, and the remaining bits

(3 through 0) indicate the device revision as shown in

Table 4

below.

7.2

Power Control - Address 02h

7.2.1

Freeze (Bit 7)

Function:

This function allows modifications to be made to certain control port bits without the changes taking effect

until the Freeze bit is disabled. To make multiple changes to these bits take effect simultaneously, set the

Freeze bit, make all changes, then clear the Freeze bit. The bits affected by the Freeze function are listed

Table 5

7.2.2

Power-Down MIC (Bit 3)

Function:

The microphone preamplifier block will enter a low-power state whenever this bit is set.

7.2.3

Power-Down ADC (Bit 2)

Function:

The ADC pair will remain in a reset state whenever this bit is set.

7.2.4

Power-Down Device (Bit 0)

Function:

The device will enter a low-power state whenever this bit is set. The power-down bit is set by default and

must be cleared before normal operation can occur. The contents of the control registers are retained

when the device is in power-down.

PART3

PART2

PART1

PART0

REV3

REV2

REV1

REV0

REV[3:0]

Revision

0000

Table 4. Device Revision

Freeze

Reserved

PDN_MIC

PDN_ADC

Reserved

PDN

Name

Register

Bit(s)

Mute

04h

Gain[5:0]

07h

5:0

Gain[5:0]

08h

5:0

Table 5. Freeze-able Bits

Summary of Contents for CS5346

Page 1: ...and microphone level inputs The microphone input path includes a 32 dB gain stage and a low noise bias voltage supply The PGA is avail able for line or microphone inputs and provides gain attenuation of 12 dB in 0 5 dB steps The output of the PGA is followed by an advanced 5th order multi bit delta sigma modulator and digital filter ing decimation Sampled data is transmitted by the serial audio in...

Page 2: ... Input Connections 21 5 5 1 Analog Input Configuration for 1 VRMS Input Levels 21 5 5 2 Analog Input Configuration for 2 VRMS Input Levels 22 5 6 PGA Auxiliary Analog Output 23 5 7 Control Port Description and Timing 23 5 7 1 SPI Mode 23 5 7 2 I C Mode 24 5 8 Interrupts and Overflow 25 5 9 Reset 26 5 10 Synchronization of Multiple Devices 26 5 11 Grounding and Power Supply Decoupling 26 6 REGISTER...

Page 3: ...Left Justified 15 Figure 4 Format 1 24 Bit Data I S 15 Figure 5 Control Port Timing I C Format 16 Figure 6 Control Port Timing SPI Format 17 Figure 7 Typical Connection Diagram 18 Figure 8 Master Mode Clocking 20 Figure 9 Analog Input Architecture 21 Figure 10 CS5346 PGA 22 Figure 11 1 VRMS Input Circuit 22 Figure 12 1 VRMS Input Circuit with RF Filtering 22 Figure 13 2 VRMS Input Circuit 22 Figur...

Page 4: ...able 4 Device Revision 28 Table 5 Freeze able Bits 28 Table 6 Functional Mode Selection 29 Table 7 Digital Interface Formats 29 Table 8 MCLK Frequency 30 Table 9 PGAOut Source Selection 30 Table 10 Example Gain and Attenuation Settings 31 Table 11 PGA Soft Cross or Zero Cross Mode Selection 32 Table 12 Analog Input Multiplexer Selection 32 ...

Page 5: ...required signal level for the control port interface Refer to the Recommended Operating Conditions for appropriate voltages RST 6 Reset Input The device enters a low power mode when this pin is driven low AIN3A AIN3B 7 8 Stereo Analog Input 3 Input The full scale level is specified in the Analog Characteristics specifica tion table AIN2A AIN2B 9 10 Stereo Analog Input 2 Input The full scale level ...

Page 6: ... full scale level is specified in the Analog Characteristics specifica tion table PGAOUTA PGAOUTB 28 29 PGA Analog Audio Output Output Either an analog output from the PGA block or high impedance See PGAOut Source Select Bit 6 on page 30 NC 30 31 No Connect These pins are not connected internally and should be tied to ground to minimize any potential coupling effects AGND 32 Analog Ground Input Gr...

Page 7: ...d 30 VA NC This pin may be connected to the analog supply voltage The decoupling capacitor for the CS5345 is not required 31 AGND NC This pin should be connected to ground 35 TSTO NC This pin may be left unconnected 36 VLS VLS Serial Audio Interface Power Input Limited to nominal 5 or 3 3 V 37 TSTI NC This pin should be tied to ground 46 VD VD Digital Power Input Limited to nominal 3 3 V 1 2 3 4 5...

Page 8: ...Parameters Symbol Min Nom Max Units DC Power Supplies Analog Digital Logic Serial Port Logic Control Port VA VD VLS VLC 4 75 3 13 3 13 3 13 5 0 3 3 3 3 3 3 5 25 3 47 5 25 5 25 V V V V Ambient Operating Temperature Power Applied Commercial TA 40 85 C Parameter Symbol Min Max Units DC Power Supplies Analog Digital Logic Serial Port Logic Control Port VA VD VLS VLC 0 3 0 3 0 3 0 3 6 0 3 63 6 0 6 0 V ...

Page 9: ...evel Inputs A weighted unweighted Note 3 40 kHz bandwidth unweighted 97 94 103 100 98 dB dB dB Total Harmonic Distortion Noise Line Level Inputs Note 4 1 dB 20 dB 60 dB Note 3 40 kHz bandwidth 1 dB THD N 95 80 40 92 89 dB dB dB dB Dynamic Range Mic Level Inputs A weighted Note 3 unweighted 77 74 83 80 dB dB Total Harmonic Distortion Noise Mic Level Inputs Note 4 1 dB 20 dB Note 3 60 dB THD N 80 60...

Page 10: ...channel Input Impedance Mismatch 5 Analog Outputs Dynamic Range Line Level Inputs A weighted unweighted 98 95 104 101 dB dB Total Harmonic Distortion Noise Line Level Inputs Note 6 1 dB 20 dB 60 dB THD N 80 81 41 74 dB dB dB Dynamic Range Mic Level Inputs A weighted unweighted 77 74 83 80 dB dB Total Harmonic Distortion Noise Mic Level Inputs Note 6 1 dB 20 dB 60 dB THD N 74 60 20 68 dB dB dB Freq...

Page 11: ...5688 Fs Stopband Attenuation 70 dB Total Group Delay Fs Output Sample Rate tgd 12 Fs s Double Speed Mode Passband 0 1 dB 0 0 4896 Fs Passband Ripple 0 025 dB Stopband 0 5604 Fs Stopband Attenuation 69 dB Total Group Delay Fs Output Sample Rate tgd 9 Fs s Quad Speed Mode Passband 0 1 dB 0 0 2604 Fs Passband Ripple 0 025 dB Stopband 0 5000 Fs Stopband Attenuation 60 dB Total Group Delay Fs Output Sa...

Page 12: ... Power Supply Current VA 5 V Normal Operation VD VLS VLC 3 3 V IA ID 41 23 50 28 mA mA Power Supply Current VA 5 V Power Down Mode Note 9 VLS VLC VD 3 3 V IA ID 0 50 0 54 mA mA Power Consumption Normal Operation VA 5 V VD VLS VLC 3 3 V Power Down Mode VA 5V VD VLS VLC 3 3 V 205 76 4 2 250 93 mW mW mW Power Supply Rejection Ratio 1 kHz Note 10 PSRR 55 dB VQ Characteristics Quiescent Voltage VQ 0 5 ...

Page 13: ...ameters Note 11 Symbol Min Typ Max Units High Level Input Voltage Serial Port Control Port VIH VIH 0 7xVLS 0 7xVLC V V Low Level Input Voltage Serial Port Control Port VIL VIL 0 3xVLS 0 3xVLC V V High Level Output Voltage at Io 2 mA Serial Port Control Port VOH VOH VLS 1 0 VLC 1 0 V V Low Level Output Voltage at Io 2 mA Serial Port Control Port VOL VOL 0 4 0 4 V V Input Leakage Current Iin 10 A In...

Page 14: ...requency fmclk 2 048 51 200 MHz MCLK Input Pulse Width High Low tclkhl 8 ns Master Mode LRCK Duty Cycle 50 SCLK Duty Cycle 50 SCLK falling to LRCK edge tslr 10 10 ns SCLK falling to SDOUT valid tsdo 0 36 ns Slave Mode LRCK Duty Cycle 40 50 60 SCLK Period Single Speed Mode Double Speed Mode Quad Speed Mode tsclkw tsclkw tsclkw ns ns ns SCLK Pulse Width High tsclkh 30 ns SCLK Pulse Width Low tsclkl ...

Page 15: ...erial Audio Port Timing Figure 2 Slave Mode Serial Audio Port Timing Figure 3 Format 0 24 Bit Data Left Justified LRCK SCLK SDATA 3 2 1 5 4 1 2 3 4 5 3 2 1 5 4 MSB 1 2 3 4 Channel A Left Channel B Right LSB LSB MSB Figure 4 Format 1 24 Bit Data I S LRCK SCLK SDATA 3 2 1 5 4 MSB 1 2 3 4 5 3 2 1 5 4 1 2 3 4 Channel A Left Channel B Right LSB MSB LSB ...

Page 16: ...or to first clock pulse thdst 4 0 µs Clock Low time tlow 4 7 µs Clock High Time thigh 4 0 µs Setup Time for Repeated Start Condition tsust 4 7 µs SDA Hold Time from SCL Falling Note 13 thdd 0 µs SDA Setup time to SCL Rising tsud 250 ns Rise Time of SCL and SDA trc trd 1 µs Fall Time SCL and SDA tfc tfd 300 ns Setup Time for Stop Condition tsusp 4 7 µs Acknowledge Delay from SCL Falling tack 300 10...

Page 17: ... High Time Between Transmissions tcsh 1 0 s CS Falling to CCLK Edge tcss 20 ns CCLK Low Time tscl 66 ns CCLK High Time tsch 66 ns CDIN to CCLK Rising Setup Time tdsu 40 ns CCLK Rising to DATA Hold Time Note 14 tdh 15 ns CCLK Falling to CDOUT Stable tpd 50 ns Rise Time of CDOUT tr1 25 ns Fall Time of CDOUT tf1 25 ns Rise Time of CCLK and CDIN Note 15 tr2 100 ns Fall Time of CCLK and CDIN Note 15 tf...

Page 18: ...ght Analog Input 1 AIN2A Left Analog Input 2 AIN2B Right Analog Input 2 AIN3A Left Analog Input 3 AIN3B Right Analog Input 3 AIN4A MICIN1 Left Analog Input 4 AIN4B MICIN2 Right Analog Input 4 AIN5A Left Analog Input 5 AIN5B Right Analog Input 5 AIN6A Left Analog Input 6 AIN6B Right Analog Input 6 MICBIAS AGND 0 1 µF NC NC NC NC NC NC NC NC NC 10 µF 3 3V 0 1 µF 10 µF 0 1 µF VA VD 5V RL See Note 2 C...

Page 19: ...out of the device TheFM bits See Func tional Mode Bits 7 6 on page 29 and the MCLK Freq bits See MCLK Frequency Address 05h on page 30 configure the device to generate the proper clocks in Master Mode and receive the proper clocks in Slave Mode Table 2 illustrates several standard audio sample rates an d the required MCLK and LRCK frequencies Mode Sampling Frequency Single Speed 8 50 kHz Double Sp...

Page 20: ...yielding clicks when switching between devices in a mul tichannel system The high pass filter continuously subtracts a measure of the DC offset from the output of the decimation filter If the HPFFreeze bit See High Pass Filter Freeze Bit 1 on page 29 is set during normal operation the current value of the DC offset for the each channel is frozen and this DC offset will continue to be sub tracted f...

Page 21: ...al filter will reject sig nals within the stopband of the filter However there is no rejection for input signals which are n 6 144 MHz the digital passband frequency where n 0 1 2 Refer to the Typical Connection Diagram for the recommended analog input circuit that will attenuate noise energy at 6 144 MHz The use of capac itors which have a lar ge voltage coefficient such as ge neral purpose ceram...

Page 22: ...ternal 12 k resistor and the input impedance to the network is increased to 48 k The PGA gain must also be configured to attenuate the 1 5 VRMS at the input pin to the 1 0 VRMS maximum A D input level to prevent clipping in the ADC 36 k VCM 9 k to 144 k A D Input Analog Input CS5346 Figure 10 CS5346 PGA 36 k VCM 9 k to 144 k A D Input 2 2 µF 100 k Analog Input CS5346 Figure 11 1 VRMS Input Circuit...

Page 23: ...s two modes SPI and I C with the CS5346 acting as a slave device SPI Mode is se lected if there is a high to low transition on the AD0 CS pin after the RST pin has been brought high I C Mode is selected by connecting the AD0 CS pin through a resistor to VLC or DGND thereby permanently selecting the desired AD0 bit address state 5 7 1 SPI Mode In SPI Mode CS is the chip select signal CCLK is the co...

Page 24: ...d low for a write The upper 5 bits of the 7 bit address field are fixed at 10011 To communicate with a CS5346 the chip address field which is the first byte sent to the CS5346 should match 10011 followed by the settings of the AD1 and AD0 The 8th bit of the address is the R W bit If the operation is a write the next byte is the Memory Address Pointer MAP which selects the register to be read or wr...

Page 25: ...herals connected to the microcontroller interrupt input pin In this configuration an ex ternal pull up resistor must be placed on the INT pin for proper operation Many conditions can cause an interrupt as listed in the interrupt status register descriptions see Inter rupt Status Address 0Dh on page 35 Each source may be masked off through mask register bits In addition Each source may be set toris...

Page 26: ...f or all of the CS5346s in the system If only one master clock source is needed one solution is to place one CS5346 in Master Mode and slave all of the other CS5346s to the one master If multiple master clock sources are needed a possible solution would be to supply all clocks from the same external source and time the CS5346 reset with the inactive edge of master clock This will ensure that all c...

Page 27: ... Gain Control Reserved Reserved Gain5 Gain4 Gain3 Gain2 Gain1 Gain0 pg 30 0 0 0 0 0 0 0 0 08h PGA Ch A Gain Control Reserved Reserved Gain5 Gain4 Gain3 Gain2 Gain1 Gain0 pg 31 0 0 0 0 0 0 0 0 09h Analog Input Control Reserved Reserved Reserved PGASoft PGAZero Sel2 Sel1 Sel0 pg 31 0 0 0 1 1 0 0 1 0Ah 0Bh Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved 0 0 0 0 0 0 0 ...

Page 28: ...nction are listed in Table 5 7 2 2 Power Down MIC Bit 3 Function The microphone preamplifier block will enter a low power state whenever this bit is set 7 2 3 Power Down ADC Bit 2 Function The ADC pair will remain in a reset state whenever this bit is set 7 2 4 Power Down Device Bit 0 Function The device will enter a low power state whenever this bit is set The power down bit is set by default and...

Page 29: ...s filter is disabled The current DC offset value will be frozen and continue to be subtracted from the conversion result See High Pass Filter and DCOffset Calibration on page 20 7 3 5 Master Slave Mode Bit 0 Function This bit selects either master or slave operation for the serial audio port Setting this bit selects Master Mode while clearing this bit selects Slave Mode 7 6 5 4 3 2 1 0 FM1 FM0 Res...

Page 30: ... Control Address 07h 7 6 1 Channel B PGA Gain Bits 5 0 Function See Channel A PGA Gain Bits 5 0 on page 31 7 6 5 4 3 2 1 0 Reserved MCLK Freq2 MCLK Freq1 MCLK Freq0 Reserved Reserved Reserved Reserved MCLK Divider MCLK Freq2 MCLK Freq1 MCLK Freq0 1 0 0 0 1 5 0 0 1 2 0 1 0 3 0 1 1 4 1 0 0 Reserved 1 0 1 Reserved 1 1 x Table 8 MCLK Frequency 7 6 5 4 3 2 1 0 Reserved PGAOut Reserved Reserved Reserved...

Page 31: ...gnal zero crossing to minimize audible artifacts The requested level change will occur after a time out period between 512 and 1024 sample periods 10 7 ms to 21 3 ms at 48 kHz sample rate if the signal does not encounter a zero crossing The zero cross function is independently monitored and implemented for each channel See Table 11 Soft Ramp and Zero Cross Enable Soft Ramp and Zero Cross Enable di...

Page 32: ...ce the last reading of the register Status bits that are masked off in the associated mask register will always be 0 in this register This register defaults to 00h PGASoft PGAZeroCross Mode 0 0 Changes to affect immediately 0 1 Zero Cross enabled 1 0 Soft Ramp enabled 1 1 Soft Ramp and Zero Cross enabled default Table 11 PGA Soft Cross or Zero Cross Mode Selection Sel2 Sel1 Sel0 PGA ADC Input 0 0 ...

Page 33: ...s align with the corresponding bits in the Status register 7 12 Status Mode MSB Address 0Fh 7 13 Status Mode LSB Address 10h Function The two Status Mode registers form a 2 bit code for each Status register function There are three ways to update the Status register in accordance with the status condition In the Rising Edge Active Mode the sta tus bit becomes active on the arrival of the condition...

Page 34: ...ls Total Harmonic Distortion Noise The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified bandwidth typically 10 Hz to 20 kHz including distortion components Expressed in decibels Measured at 1 and 20 dBFS as suggested in AES17 1991 Annex A Frequency Response A measure of the amplitude response variation from 10 Hz to 20 kHz relative to the ampl...

Page 35: ...60 50 40 30 20 10 0 0 40 0 42 0 44 0 46 0 48 0 50 0 52 0 54 0 56 0 58 0 60 Frequency normalized to Fs Amplitude dB 10 9 8 7 6 5 4 3 2 1 0 0 45 0 46 0 47 0 48 0 49 0 5 0 51 0 52 0 53 0 54 0 55 Frequency normalized to Fs Amplitude dB 0 10 0 08 0 06 0 04 0 02 0 00 0 02 0 04 0 06 0 08 0 10 0 0 05 0 1 0 15 0 2 0 25 0 3 0 35 0 4 0 45 0 5 Frequency normalized to Fs Amplitude dB 140 130 120 110 100 90 80 ...

Page 36: ...0 15 0 20 0 25 0 30 0 35 0 40 0 45 0 50 Frequency normalized to Fs Amplitude dB 140 130 120 110 100 90 80 70 60 50 40 30 20 10 0 0 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 8 0 9 1 0 Frequency normalized to Fs Amplitude dB 140 130 120 110 100 90 80 70 60 50 40 30 20 10 0 0 20 0 25 0 30 0 35 0 40 0 45 0 50 0 55 0 60 0 65 0 70 0 75 0 80 0 85 Frequency normalized to Fs Amplitude dB 10 9 8 7 6 5 4 3 2 1 0 0 10 ...

Page 37: ...0 354 0 366 8 70 9 0 BSC 9 30 D1 0 272 0 28 0 280 6 90 7 0 BSC 7 10 E 0 343 0 354 0 366 8 70 9 0 BSC 9 30 E1 0 272 0 28 0 280 6 90 7 0 BSC 7 10 e 0 016 0 020 0 024 0 40 0 50 BSC 0 60 L 0 018 0 24 0 030 0 45 0 60 0 75 0 000 4 7 000 0 00 4 7 00 Nominal pin pitch is 0 50 mm Controlling dimension is mm JEDEC Designation MS022 Parameters Symbol Min Typ Max Units Package Thermal Resistance Note 1 48 LQF...

Page 38: ...ird parties This document is the property of Cirrus and by furnishing this information Cirrus grants no license express or implied under any patents mask work rights copyrights trademarks trade secrets or other intellectual property rights Cirrus owns the copyrights associated with the information contained herein and gives consent for copies to be made of the information only for use within your ...

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