Cirrus Logic CS5346, Manual

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26 DS861PP3
CS5346
5.9 Reset
When RST is low, the CS5346 enters a low-power mode and all internal states are reset, including the con-
trol port and registers, the outputs are muted. When RST is high, the control port becomes operational, and
the desired settings should be loaded into the control registers. Writing a 0 to the PDN bit in the Power Con-
trol register will then cause the part to leave the low-power state and begin operation.
The delta-sigma modulators settle in a matter of microseconds after the analog section is powered, either
through the application of power or by setting the RST pin high. However, the voltage reference will take
much longer to reach a final value due to the presence of external capacitance on the FILT+ pin. During this
voltage reference ramp delay, SDOUT will be automatically muted.
It is recommended that RST be activated if the analog or digital supplies drop below the recommended op-
erating condition to prevent power-glitch-related issues.
5.10 Synchronization of Multiple Devices
In systems where multiple ADCs are required, care must be taken to achieve simultaneous sampling. To
ensure synchronous sampling, the mast er clocks and left/ right clocks must be the same f or all of the
CS5346s in the system. If only one master clock source is needed, one solution is to place one CS5346 in
Master Mode, and slave all of the other CS5346s to the one master. If multiple master clock sources are
needed, a possible solution would be to supply all clocks from the same external source and time the
CS5346 reset with the inactive edge of master clock. This will ensure that all converters begin sampling on
the same clock edge.
5.11 Grounding and Power Supply Decoupling
As with any high-resolution converter, the CS5346 requires careful attention to power supply and grounding
arrangements if its potential performance is to be realized. Figure 7 shows the recommended power ar-
rangements, with VA connected to a clean supply. VD, which powers the digital filter, may be run from the
system logic supplies (VLS or VLC). Power supply decoupling capacitors should be as near to the CS5346
as possible, with the low value ceramic capacitor being the nearest. All signals, especially clocks, should be
kept away from the FILT+ and VQ pins in order to avoid unwanted coupling into the modulators. The FILT+
and VQ decoupling capacitors, particularly the 0.1 µF, must be positioned to minimize the electrical path
from FILT+ and AGND. The CS5346 evaluation board demonstrates the optimum layout and power supply
arrangements. To minimize digital noise, connect the CS5346 digital outputs only to CMOS inputs.