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DKHiQV-PCI (Fab. Rev. B) User’s Guide
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DKHiQV-PCI (Fab. Rev. B) Subject to Change Without Notice
Revision 1.3 7/2/99
6.2
Programmable Linear Acceleration
The DKHiQV-PCI based board improves graphics performance by supporting a programmable linear ad-
dressing mode to take advantage of CHIPS 32-bit linear acceleration drivers. The programmable ’Linear
Acceleration’ video memory provides the ability to ’linearly map’ the video memory to anywhere in the 32-
bit system memory in 8MB increments, thus overcoming paging and I/O bottlenecks. High performance lin-
ear acceleration drivers are available for popular application programs such as Windows
.
The user can enable or disable linear addressing using configuration bit XR0A[1]. The user can also specify
the desired video buffer start address using PCI configuration register MBASE. When reset, the linear ad-
dressing mode is disabled and the base addresses of the video memory is at A000:0 See the PCI config-
uration section for additional information.
6.3
Memory Interface
For the B65555, the ABHiQV daughtercard is designed to support 256K x 32 EDO memory in the 100pin
PQFP mechanical package. Refer to Tables 4-1 for the resistor connections for EDO configurations.
Note: C is connected and NC is not connected.
Table 4-1: Resistor Connections for EDO Configuration
EDO
CONFIGURATION
R1
NC
R2
NC
R9
C
R14
NC
R15
NC
R16
NC
R17
NC
R18
C
R19
NC
