25
DKHiQV-PCI (Fab. Rev. B) User’s Guide
&+,36
DKHiQV-PCI (Fab. Rev. B) Subject to Change Without Notice
Revision 1.3 7/2/99
Table 10: ABHiQV (Fab. Rev. C) Daughtercard Configuration Settings for B65555 TV Out & Mul-
timedia Disabled
Note: Refer to Figure 1 for jumper locations.
Notes:
*Schematic reference and functional category.
**’on’ - jumper plug installed.
’off’ - jumper plug is not installed.
Table 11: DKHiQV-PCI Jumper Configuration Settings for TV Out Enabled on 69xxx and B65555
Note: Refer to Figure 2 for jumper locations.
Notes:
*Schematic reference and functional category.
**’on’ - jumper plug installed.
’off’ - jumper plug is not installed.
1.
For PAL, U1/U4 on DKHiQV-PCI DK board must be replaced with a 17.7344 MHz crystal oscillator.
2.
Using BMP utility, change RAM BIOS to enable TV through GPIO 0 and enable output composite
sync in NTSC/PAL
Jumper
Function*
State**
W1
sh.1, EXT CLK
off
W2
sh.1, BVCC55X
off
W3
sh.1, ACTI/ENABLK
off
W4
sh.1, TMD 0
off
W5
sh.1, TMD 1
off
W6
sh.1, MVCC55X
2-3
Switch Position
Function*
State**
S1[1]
sh.1, CFG 15
off
S1[2]
sh.1, PID 3
off
S1[3]
sh.1, PID 2
off
S1[4]
sh.1, PID1
off
S1[5]
sh.1, PID 0
off
S1[6]
sh.1, PCI
off
S1[7]
sh.1, CLK - TST
off
S1[8]
sh.1, CFG 9
off
Jumper
NTSC
2
Function*
State**
Jumper
PAL
1,2
Function*
State**
W2
sh.5 TV OUT
off
W2
sh.5 TV OUT
off
W4
sh.5 TV OUT
2-3
W4
sh.5 TV OUT
1-2
W5
sh.2, ENTV controlled by
SDA; GPIO 0
2-3
W5
sh.2, ENTV controlled by SDA;
GPIO 0
2-3
W6
sh.5 TV OUT, NTSC
off
W6
sh.5 TV OUT, NTSC
on
W8
sh.2, TV OUT, TSYNC
off
W8
sh.2, TV OUT, TSYNC
off
JP1
sh.5 TV OUT
on
JP1
sh.5 TV OUT
on
JP2
sh.5 TV OUT
on
JP2
sh.5 TV OUT
on
JP3
sh.5 TV OUT
on
JP3
sh.5 TV OUT
on
JP13
sh.2, CYSYNC/HSYNC
on
JP13
sh.2, CYSYNC/HSYNC
on
