DKHiQV-PCI (Fab. Rev. B) User’s Guide
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DKHiQV-PCI (Fab. Rev. B) Subject to Change Without Notice
Revision 1.3 7/2/99
4.1 Configuration Switch (S1) and Jumpers (W1 and W3)
The ABHiQV provides one on-board Dip Switch S1 and two jumpers W1 and W2 for various configuration
settings. There are three configuration bits (CFG7,4,1) which are latched from AA7,4,1 on reset. CFG7,4,1
are written into the HiQVideo
controller extended register XR70[7:0].
Four additional configuration bits, CGF14:11 are latched into XR71[6:3] from MAD[6:3] on reset. The soft-
ware reserves these configuration bits for input of panel IDs. They correspond to DIP switch S1 positions
5:2 on the ABHiQV daughtercard.
All CFG pins have internal weak pull up and may be pulled down by 4.7k resistors on the daughtercard if
the DIP switches are set to ON. Table 1 summarizes all the CFG bits and corresponding DIP switches and
jumpers W1 and W3.
Refer to the applicable databook for additional configuration options.
Table 1: Configuration Settings
Bits
Latched
From
Name
Purpose
XR Bits
Daughtercard DIP
Switch Position and
Defaults
CFG0
AA0
Reserved
XR70[0]
CFG1
AA1
PCI
VGA I/O Decoding
Enable/Disable on
PCI bus
XR70[1]
S1[6]: open
CFG2
AA2
Reserved
XR70[2]
CFG3
AA3
Reserved
XR70[3]
CFG4
AA4
Ext. CLK
External OSC for
MCLK and DCLK
XR70[4]
W1: open
CFG5
AA5
Reserved
XR70[5]
CFG6
AA6
Reserved
ACTI/ENABKL
XR70[6]
W3: open
CFG7
AA7
CLK-TST
Internal clock test
mode disable
XR70[7]
S1[7]: open
CFG8
AA8
Reserved
XR71[0]
CFG10
MA 2
Reserved
XR71[2]
CFG11
MA 3
PID0
Panel Type
XR71[3]
S1[5]: open
CFG12
MA 4
PID1
Panel Type
XR71[4]
S1[4]: open
CFG13
MA 5
PID2
Panel Type
XR71[5]
S1[3]: open
CFG14
MA 6
PID3
Panel Type
XR71[6]
S1[2]: open
