CHIPS DKHiQV-PCI User Manual Download Page 3

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DKHiQV-PCI (Fab. Rev. B) Subject to Change Without Notice

Revision 1.3 7/2/99

Revision History

Revision

Date

Comment

1.0

10/22/97

RG/lnc

Initial release for Fab. Rev. B Boards.

1.1

7/22/98

RG/bjb

Amended to highlight 69000 and 65555.

1.3 7/2//99

AP/dak Added ABHiQV Fab. Rev. C and all 69xxx devices.

Summary of Contents for DKHiQV-PCI

Page 1: ...DKHiQV PCI Fab Rev B HiQVideo Series PCI Board User s Guide Revision 1 3 July 1999 36 ...

Page 2: ...rk of Intel Corporation HiQVideo is a trademark of Intel Corporation All other trademarks are the property of their respective holders 3DQHO LQN technology is licensed by Intel Corporation from Silicon Image Inc of Palo Alto CA 3DQHO LQN is a trademark of Silicon Image Inc Disclaimer This document provides general information for the customer Intel Corporation reserves the right to modify the info...

Page 3: ...out Notice Revision 1 3 7 2 99 Revision History Revision Date By Comment 1 0 10 22 97 RG lnc Initial release for Fab Rev B Boards 1 1 7 22 98 RG bjb Amended to highlight 69000 and 65555 1 3 7 2 99 AP dak Added ABHiQV Fab Rev C and all 69xxx devices ...

Page 4: ...1 6 4 Display Interface 13 6 4 1 Flat Panel Interface 13 6 4 2 CRT Interface 14 6 5 Clock 16 6 5 1 14MHz Reference Clock 16 6 5 2 32KHz Clock 16 6 6 PCI Configuration 16 6 7 BIOS Interface 16 6 8 NTSC PAL Composite Video Output TV out 16 6 9 Multimedia Card Interface 17 6 10 MPEG and ZV Port Connector 18 6 11 Activity Indicator 18 6 12 Mixed Voltage Generation and Power Measurement 19 6 13 Power S...

Page 5: ...Configuration 11 Table 4 2 EDO Memory Configuration Types for B65555 12 Table 5 Flat Panel Connection Summary 15 Table 6 Video Sub System Voltages 19 Table 7 DKHiQV PCI Rev B Board Configuration Settings for 69xxx TV Out and Multimedia Disabled 22 Table 8 ABHiQV Fab Rev C Daughtercard Configuration Settings for 69xxx TV Out and Multimedia Disabled 23 Table 9 DKHiQV PCI Rev B Board Configuration Se...

Page 6: ...te the design kit This User s Guide describes the man DK board The use of a B65555 or 69xxx HiQVideo accelerator on an ABHiQV daughtercard is also described in the ABHiQV User s Guide The DKHiQVPCI based board is a full size PCI add in card It has bus connectors to interface with the PCI Bus at speeds up to 33MHz The multiple jumper configurations and connectors allow the DK board to test performa...

Page 7: ...er supplies individually configurable to 3 3V and 5V for different blocks of the video sub system Onboard power sequencing VGA to NTSC PAL conversion to provide S VHS video and composite video outputs Interrupt signal added for 69xxx support INT to INTA on PCI bus TV out and CRT enable disable under software control Note Limited solution CRT HSYNC VSYNC only not RGB ACT125 buffer for CSYNC to TV o...

Page 8: ...to Fig ures 1 and 2 for jumper locations Note For TV out and multimedia settings refer to Tables 11 and 12 6 Plug the ABHiQV Fab Rev C daughtercard onto the DKHiQV PCI based board The connectors header in the ABHiQV daughtercard is composed of eight 2X16 header socket type pins P1 7 Power down the host system and plug the DKHiQV PCI based board into an available PCI slot on the motherboard Please ...

Page 9: ...DKHiQV PCI Fab Rev B Configuration Compo nents Figure 1 shows the location of the components used to configure the ABHiQV Fab Rev B daughtercard front view rear view Figure 1 Component Location MA0 RP1 GND3 GND4 GND2 GND1 MA1 W 6 W 5 W 4 W 3 W 2 S1 W 1 U8 U1 U7 U5 U6 U3 U4 U2 U4 U3 U6 U5 1 2 3 AB65555 QEDO AB65560 SD AB65560 QEDO AB69000 ...

Page 10: ...deo J1 S Video W 1 J2 Access Bus JP1 JP2 JP3 W 40 W 8 W 7 W 9 W 6 W 5 W 3 W 4 JP10 JP5 JP11 JP9 JP7 JP8 JP6 JP12 JP13 W 37 W 36 JP4 W 21 W 39 W 38 J5 Panel Connection J10 J8 J9 W 23 J7 MPEG Connection J11 Panel Conn II R76 R75 W 35 SH4 W 34 W 32 W 33 W 31 W 30 W 29 W 28 W 27 SH6 SH5 SH7 W 24 W 25 W 26 R59 R82 W 10 W 12 W 13 W 14 W 15 W 16 W 17 W 18 W 19 W 20 JP19 JP15 JP16 JP18 JP20 JP17 ...

Page 11: ... down by 4 7k resistors on the daughtercard if the DIP switches are set to ON Table 1 summarizes all the CFG bits and corresponding DIP switches and jumpers W1 and W3 Refer to the applicable databook for additional configuration options Table 1 Configuration Settings Bits Latched From Name Purpose XR Bits Daughtercard DIP Switch Position and Defaults CFG0 AA0 Reserved XR70 0 CFG1 AA1 PCI VGA I O D...

Page 12: ...AT DDCC0LK are pulled up to DVCC55X DDCDAT DDCC0LK are pulled up to GVCC W8 OPEN CLOSED External video encoder uses TSYNC held high External video encoder uses TSYNC derived from VSYNC W9 1 2 2 3 EPROM power is from 3V main 3V EPROM power is from GVCC 5V W10 OPEN CLOSED Combined with W11 provides card present and power requirement information to system See PCI spec for details W11 OPEN CLOSED See ...

Page 13: ...voltage is 3 3V from the PCI connector W36 1 2 2 3 CVCC from 3VMAIN CVCC from 5VNC W37 1 2 2 3 PCLK goes to panel connector J5 instead of M for 3DQHO LQN STN DD M goes to panel connector J5 W38 1 2 2 3 VDDSAFE uses GVCC 5V VDDSAFE uses 3VMAIN W35 W39 1 2 2 3 VEESAFE is controlled by R82 potrentiometer VEESAFE is controlled by W21 W40 OPEN CLOSED 69xxx INT disconnected from INTA on PCI bus 69xxx IN...

Page 14: ...IO0 CSYNC JP9 1 2 2 3 3 4 1 4 JP9 JP10 pin 1 is driven by 32KHZ GPIO1 GPIO2 JP9 pin 3 is driven by 32KHZ GPIO1 CSYNC JP9 pin 3 is driven by ENABKL GPIO1 CSYNC JP9 JP10 pin 1 is driven by ENABKL GPIO1 CSYNC JP10 1 2 2 3 3 4 1 4 JP9 JP10 pin 1 is driven by 32KHZ GPIO1 GPIO2 32 KHz oscillator drives 32KHZ GPIO1 GPIO2 signal NOT VALID JP9 JP10 pin 1 is driven by 54GPIO2 JP11 1 2 2 3 3 4 1 4 ENAVEE pan...

Page 15: ... to evaluate all the following HiQVideo interfaces bus flat panel CRT memory MPEG multimedia card and composite video The boards also provide a mixed voltage capability with the ability to measure power for different blocks of the video subsystem The minimal component video sub system consists of the HiQVideo chip and two blocks of DRAM U3 and U5 Refer to the B65555 and 69xxx HiQVideo Data Books f...

Page 16: ... for popular application programs such as Windows The user can enable or disable linear addressing using configuration bit XR0A 1 The user can also specify the desired video buffer start address using PCI configuration register MBASE When reset the linear ad dressing mode is disabled and the base addresses of the video memory is at A000 0 See the PCI config uration section for additional informati...

Page 17: ... XR42 2 and the DRAM data bus width through XR43 4 5 for the B65555 The tables below show the possible configurations Note XR41 01h for EDO memory XR42 00h for 256 wide column and XR43 10h for 64 bit interface Table 4 2 EDO Memory Configuration Types for B65555 SIZE BANDWIDTH ORGANIZATION Qty needed Modules 2 MB 64 bit single bank 256Kx32 2 U3 U5 4 MB 64 bit dual bank 256Kx32 4 U3 U4 U5 U6 ...

Page 18: ... flat panel and CRT display The HiQVideo control lers do not need an additional frame buffer for simultaneous display of CRT and single scan flat panel dis plays such as TFT color panels including 24 bit or plasma and EL panels For LCD DD panels the HiQVideo controllers can support simultaneous display with 60 Hz vertical refresh on both the CRT and flat panel or even 60 Hz vertical refresh on the...

Page 19: ...connector J4 The DKHiQV PCI based board supports non interlaced CRT monitors with resolutions up to 1280x1024 with 16 million colors at 75 Hz Table 5 summarizes the HiQVideo pin connections for the different flat panel configurations Refer to the 65555 and 69xxx Databooks for the 36 pin panel support information and pin assignments Name Pin Pin Name GND 1 2 P24 GND 3 4 P25 GND 5 6 P26 GND 7 8 P27 ...

Page 20: ... G1 B6 B12 B2 R4 LB0 LB0 U9 P7 25 P7 LD0 UD0 G2 B7 B13 G2 B4 LR1 LR1 V9 P8 27 LD7 G3 G0 G00 B2 SHFCLKU UG1 Y9 P9 28 LD6 G4 G1 G01 R3 UB1 V10 P10 30 LD5 G5 G2 G02 G3 UR2 Y9 P11 31 LD4 R0 G3 G03 B3 UG2 V10 P12 33 LD3 R1 G4 G10 R4 LG1 W10 P13 34 LD2 R2 G5 G11 G4 LB1 Y10 P14 36 LD1 R3 G6 G12 B4 LR2 U10 P15 37 LD0 R4 G7 G13 R5 LG2 U11 P16 39 R0 R00 W11 P17 40 R1 R01 Y11 P18 42 R2 R02 V11 P19 43 R3 R03 ...

Page 21: ...nfiguration address space for this pur pose For the PCI Bus configuration the HiQVideo controllers use ten registers to identify the chip ex amine the various internal states configure the video memory and BIOS ROM base addresses and control the settings for the various operating modes These registers are located in the PCI configuration space The HiQVideo controllers support both I O mapped memor...

Page 22: ...shows the multimedia connector pins Refer to Table 12 for multimedia settings Figure 5 Media Connector Pinout J8 J10 Name Pin Pin Name Name Pin Pin Name GND 1 2 Y0 GND 1 2 UV0 GND 3 4 Y1 GND 3 4 UV1 GND 5 6 Y2 GND 5 6 UV2 GND 7 8 Y3 GND 7 8 UV3 GND 9 10 Y4 GND 9 10 UV4 GND 11 12 Y5 GND 11 12 UV5 GND 13 14 Y6 GND 13 14 UV6 GND 15 16 Y7 GND 15 16 UV7 GND 17 18 HREF GND 17 18 SDA GND 19 20 VREF GND 1...

Page 23: ...put is an active high signal which is driven high every time the CPU executes a valid VGA memory read write operation or VGA I O read write operation The DKHiQV PCI based board has an LED D7 on the ACTI pin which will glow whenever there is a VGA access This pin is configured as Activity Indicator by default when FR0C 4 3 00 The power management logic may use this signal to put the HiQVideo contro...

Page 24: ...ontrol Flat panel displays are extremely sensitive to conditions where full biasing voltage VEESAFE is applied to the liquid crystal material without enabling the control and data signals to the panel The DKHiQV PCI based board provides three controlled voltages VDDSAFE VDD for driver electronics VEESAFE VEE for LCD bias and 12VSAFE BACKLIGHT for easy access for most panels The power sequencing co...

Page 25: ... 3DQHO LQN and LVDS Interfaces The DK board allows a 3DQHO LQN or LVDS transmitter adapter card to be installed in the panel connector J5 Various jumper options allow flexible selection of 3 3V or 5V power for the adapter card as well as a PCLK option for STN DD panel support via a 3DQHO LQN or LVDS interface A PCLK for 3DQHO LQN STN DD support If the 3DQHO LQN interface is operated at 3 3V as des...

Page 26: ...leshooting 1 Check that all jumpers and DIP switch positions are set to their default positions 2 Verify that socket U2 contains a PCI BIOS ROM 3 Verify that other parts in the system function properly by using a known working VGA board with the system 4 If the DKHiQV PC still does not work contact your Intel representative ...

Page 27: ... DDC pull up 2 3 W39 sh 5 VEESAFE by R82 off W8 sh 2 TV out off W40 sh 2 INT on W9 sh 2 GVCC 2 3 JP1 sh 5 CRT drive off W10 sh 3 PCI on JP2 sh 5 CRT drive off W11 sh 3 PCI off JP3 sh 5 CRT drive off W12 sh 5 VEESAFE off JP4 sh 5 Panel VCC off W13 sh 5 VEESAFE off JP5 sh 2 I2C all off W14 sh 5 VEESAFE on JP6 sh 2 I2C all off W15 sh 5 VDDSAFE on JP7 sh 2 DDC 1 2 3 4 W16 sh 5 VDDSAFE off JP8 sh 2 DDC...

Page 28: ...ocations Notes Schematic reference and functional category on jumper plug installed off jumper plug is not installed Jumper Function State W1 sh 1 EXT CLK off W2 sh 1 BVCC55X off W3 sh 1 ACTI ENABLK off W4 sh 1 TMD 0 off W5 sh 1 TMD 1 off W6 sh 1 MVCC55X 1 2 Switch Position Function State S1 1 sh 1 CFG 15 off S1 2 sh 1 PID 3 off S1 3 sh 1 PID 2 off S1 4 sh 1 PID1 off S1 5 sh 1 PID 0 off S1 6 sh 1 ...

Page 29: ... DDC pull up 2 3 W39 sh 5 VEESAFE by R82 off W8 sh 2 TV out off W40 sh 2 INT on W9 sh 2 GVCC 2 3 JP1 sh 5 CRT drive off W10 sh 3 PCI on JP2 sh 5 CRT drive off W11 sh 3 PCI off JP3 sh 5 CRT drive off W12 sh 5 VEESAFE off JP4 sh 5 Panel VCC off W13 sh 5 VEESAFE off JP5 sh 2 I2C all off W14 sh 5 VEESAFE on JP6 sh 2 I2C all off W15 sh 5 VDDSAFE on JP7 sh 2 DDC 1 2 3 4 W16 sh 5 VDDSAFE off JP8 sh 2 DDC...

Page 30: ...MP utility change RAM BIOS to enable TV through GPIO 0 and enable output composite sync in NTSC PAL Jumper Function State W1 sh 1 EXT CLK off W2 sh 1 BVCC55X off W3 sh 1 ACTI ENABLK off W4 sh 1 TMD 0 off W5 sh 1 TMD 1 off W6 sh 1 MVCC55X 2 3 Switch Position Function State S1 1 sh 1 CFG 15 off S1 2 sh 1 PID 3 off S1 3 sh 1 PID 2 off S1 4 sh 1 PID1 off S1 5 sh 1 PID 0 off S1 6 sh 1 PCI off S1 7 sh 1...

Page 31: ...ultimedia Enabled on 69xxx B65555 Note Refer to Figure 2 for jumper locations Notes Schematic reference and functional category on jumper plug installed off jumper plug is not installed Jumper Function State JP5 sh 2 I2C 1 2 3 4 JP6 sh 2 I2C all off JP7 sh 2 DDC 1 2 3 4 JP8 sh 2 DDC all off JP9 sh 2 GPIO 2 3 JP10 sh 2 GPIO 1 4 JP11 sh 2 GPIO 1 4 2 3 JP12 sh 2 GPIO off ...

Page 32: ...ct to Change Without Notice Revision 1 3 7 2 99 Intel Corporation GCD CHP3 102 Title DKHiQV PCI UG Fab Rev B 350 East Plumeria Drive Publication No UG174 3 San Jose California 95134 Stock No 050174 003 Phone 408 765 8080 Revision No 1 3 FAX 408 545 9812 Date 7 2 99 36 ...

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