Chassis Plans ATXP-875P, Technical Reference

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ATXP-875P Technical Reference Appendix A: Technical Specifications
Chassis Plans 47
Appendix A Technical Specifications
Chipsets
Core Logic
North Bridge - Intel 875P.
South Bridge – Intel 6300ESB I/O Controller Hub.
Peripheral I/O
Standard Microsystems (SMSC) LPC47M192.
BIOS
System BIOS
American Megatrends AMIBIOS.
Flash BIOS
Standard feature for System BIOS. Flash programming built into the BIOS. BIOS to be flashed is read from a
floppy.
Embedded I/O
Floppy
2 Floppies up to 2.88 MB.
IDE
The board provides four IDE interface connectors:
•
Two Parallel ATA IDE connectors, which support a total of four devices (two per connector) and
one extra connector (mini-Header 44 pin) in parallel to IDE2 for Solid State IDE disk or any 44
pin IDE device support.
•
Two Serial ATA IDE connectors, which support one device per connector.
Parallel ATA IDE Interfaces
The ICH (Hance Rapids) Parallel ATA IDE controller has two independent bus-mastering Parallel ATA
IDE interfaces that can be independently enabled. The Parallel ATA IDE interfaces support the following
modes:
•
Programmed I/O (PIO): processor controls data transfer.
•
8237-style DMA: DMA offloads the processor, supporting transfer rates of up to 16 MB/sec.
•
Ultra DMA: DMA protocol on IDE bus supporting host and target throttling and transfer rates of
up to 33 MB/sec.
•
ATA-66: DMA protocol on IDE bus supporting host and target throttling and transfer rates of up
to 66 MB/sec. ATA-66 protocol is similar to Ultra DMA and is device driver compatible.
•
ATA-100: DMA protocol on IDE bus allows host and target throttling. The ICH ATA-100 logic
can achieve read transfer rates up to 100 MB/sec and write transfer rates up to 88 MB/sec.