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ATXP-875P

Long Life Industrial Motherboard

Revision A

Technical Reference

Intel

Pentium 4

With Hyper-Threading

Embedded Processors

Intel 875P Chipset

Summary of Contents for ATXP-875P

Page 1: ...ATXP 875P Long Life Industrial Motherboard Revision A Technical Reference Intel Pentium 4 With Hyper Threading Embedded Processors Intel 875P Chipset...

Page 2: ...tion provided Chassis Plans liability shall in no event exceed the purchase price of the product purchased hereunder The foregoing limitation of liability shall be equally applicable to any service pr...

Page 3: ...y be trademarks or registered trademarks of their respective companies LIABILITY This manual is as complete and factual as possible at the time of printing however the DISCLAIMER information in this m...

Page 4: ......

Page 5: ...alling Cables 6 Power and Control Panel Cables 6 Installing Peripheral Cables 6 Index of Connectors 9 Chapter 2 AMIBIOS Setup 11 Main Setup 14 Advanced BIOS Setup 14 PCI PnP Setup 26 Boot Setup 30 Sec...

Page 6: ...nce II Chassis Plans Appendix B Flash BIOS programming and codes 63 Troubleshooting POST 64 Critical Error BEEP Codes 69 Appendix C On Board Industrial Devices 70 Post Code Display 70 Watchdog Timer 7...

Page 7: ...nt on the part of the manufacturer or any subsequent vendor They are in no way responsible for any loss or damage resulting from the use or misuse of this publication This publication and any accompan...

Page 8: ...appendixes Chapter 1 System Board Pre Configuration This chapter provides all the necessary information for installing the ATXP 875P Topics discussed include installing the CPU if necessary DRAM insta...

Page 9: ...GB DDR SDRAM PC2100 DDR 266MHz PC2700 DDR 333MHz and PC3200 DDR 400MHz featuring dual channel and dynamic mode Please refer to chapter 3 for memory details On Board I O 2 Floppies up to 2 88 MB Dual i...

Page 10: ...s Plans Conventions Used in this Manual 8 Notes Such as a brief discussion of memory types Important Information such as static warnings or very important instructions When instructed to enter keyboar...

Page 11: ...Before touching any electronic device ground yourself by touching an unpainted metal object or and highly recommended use a grounding strap Damage from static electricity is not covered by the warrant...

Page 12: ...mation There are two different categories of jumpers on the ATXP 875P A Two pin jumpers are used for binary selections such as enable disable Instructions for this type of jumper are open for no shunt...

Page 13: ...cal Reference Chapter 1 Pre Configuration Chassis Plans 3 Jumper Locations Use the diagram below and the tables on the following pages to locate and set the on board configuration jumpers Figure 1 1 J...

Page 14: ...cc 3 3Vcc JP3 1 2 2 3 Default Settings Audio Jack Output Selection The audio output on the stacked audio jack connector J12 green color can be selected to be stereo line out or stereo headphone out am...

Page 15: ...more transistors is aggravating the thermal management of the CPU As operating frequencies increase and packaging sizes decreases the power density increases and the thermal cooling solution space an...

Page 16: ...es have been properly installed Installing Cables Power and Control Panel Cables The ATXP 875P gets power from the power connectors J15 and J16 Figure 1 4 Use only ATX12V compliant power supplies with...

Page 17: ...ATXP 875P Technical Reference Chapter 1 Pre Configuration Chassis Plans 7 Figure 1 3 ATXP 875P I O Gasket...

Page 18: ...Chapter 1 Pre Configuration ATXP 875P Technical Reference 8 Chassis Plans Figure 1 4 Location of Components and Connector...

Page 19: ...J6G1 DDR Channel A DIMM Socket 1 J6G2 DDR Channel A DIMM Socket 0 J6H1 DDR Channel B DIMM Socket 1 J6H2 DDR Channel B DIMM Socket 0 J6J1 Primary IDE J6J2 Secondary IDE J7 Keyboard Mouse Header J7B1 PC...

Page 20: ...Chapter 1 Pre Configuration ATXP 875P Technical Reference 10 Chassis Plans User s Notes...

Page 21: ...codes used by the BIOS Starting BIOS Setup AMIBIOS has been integrated into many motherboards for over a decade In the past people often referred to the AMIBIOS setup menu as BIOS BIOS setup or CMOS s...

Page 22: ...ot displayed on the ezPORT key legend by default To set the Fail Safe settings of the BIOS press the F8 key on your keyboard It is located on the upper row of a standard 101 keyboard The Fail Safe set...

Page 23: ...ATXP 875P Technical Reference Chapter 2 BIOS Configuration Chassis Plans 13...

Page 24: ...play an Advanced BIOS Setup option by highlighting it using the Arrow keys All Advanced BIOS Setup options are described in this section CPU CONFIGURATION SCREEN Information about the CPU If using an...

Page 25: ...s value to allow the computer system to detect only the Primary IDE channel This includes both the Primary Master and the Primary Slave Secondary Set this value to allow the computer system to detect...

Page 26: ...onds Set this option to stop the AMIBIOS from searching for IDE devices within the specified number of seconds Basically this allows you to fine tune the settings to allow for faster boot times Adjust...

Page 27: ...condary IDE Master and Slave Settings From the IDE Configuration screen press Enter to access the sub menu for the primary and secondary IDE master and slave drives Use this screen to select options f...

Page 28: ...block mode multi sector transfers option The Optimal and Fail Safe default setting is Auto Disabled Set this value to prevent the BIOS from using Multi Sector Transfer on the specified channel The da...

Page 29: ...e 2 It has a data transfer rate of 33 3 MBs UDMA3 Allows the BIOS to use Ultra DMA mode 3 It has a data transfer rate of 44 4 MBs To use this mode it is required that an 80 conductor ATA cable is used...

Page 30: ...etting for floppy drive A is 1 44 MB 3 The Fail Safe setting for floppy drive A is 1 44 MB 3 The Optimal setting for floppy drive B is Disabled The Fail Safe setting for floppy drive B is Disabled Dis...

Page 31: ...setting is 2F8 IRQ3 The Fail Safe setting is Disabled Disabled Set this value to prevent the serial port from accessing any system resources When this option is set to Disabled the serial port physic...

Page 32: ...cation Parallel Port IRQ This option specifies the IRQ used by the parallel port The Optimal and Fail Safe default setting is 7 5 Set this value to allow the serial port to use Interrupt 5 7 Set this...

Page 33: ...ue to allow the serial port to use 3E8 as its I O port address and IRQ 5 for the interrupt address If the system will not use a serial device it is best to set this port to Disabled 2E8 IRQ7 Set this...

Page 34: ...s is the default setting Note OEMB table is used to pass POST data to the AML code during ACPI O S operations RSDT RSDT is the main ACPI table It has no fixed place in memory During the boot up proces...

Page 35: ...his option is enabled any attached USB mouse or USB keyboard can control the system even when there is no USB drivers loaded on the system Set this value to enable or disable the Legacy USB Support Th...

Page 36: ...estrict the system from giving the VGA adapter card an interrupt address The Optimal and Fail Safe default setting is Yes Yes Set this value to allow the allocation of an IRQ to a VGA adapter card tha...

Page 37: ...elect PCI Slot 4 as the location of the OffBoard PCI IDE adapter card Use this setting only if there is an IDE adapter card installed in PCI Slot 4 PCI Slot5 This setting will select PCI Slot 5 as the...

Page 38: ...ISA devices 64K Set this value to allow the system to reserve 64K of the system memory to the ISA devices Reserved Memory Address Set this value to the base address of memory block to reserve for leg...

Page 39: ...ged in the PCI Slot 4 The optimal and fail safe default is Auto Auto 3 4 5 6 7 9 10 11 12 14 15 Note Manual IRQ selection does not guarantee that the PCI slot device will be configured with the choice...

Page 40: ...y memory messages The Optimal and Fail Safe default setting is Force BIOS An example of this is a SCSI BIOS or VGA BIOS Force BIOS Set this value to allow the computer system to force a third party BI...

Page 41: ...nabled the Hit DEL message will not display Enabled This allows the ezPORT to display Hit Del to enter Setup during memory initialization This is the default setting Interrupt 19 Capture Set this valu...

Page 42: ...ord The Supervisor and User passwords activate two different levels of password security If you select password support you are prompted for a one to six character password Type the password on the ke...

Page 43: ...appears when a write is attempted to the boot sector You may have to type N several times to prevent the boot sector write Boot Sector Write Possible VIRUS Continue Y N _ The following appears after...

Page 44: ...that item You can display a Chipset BIOS Setup option by highlighting it using the Arrow keys All Chipset BIOS Setup options are described in this section NORTH BRIDGE CONFIGURATION North Bridge Chip...

Page 45: ...etting is Auto C000 16k Shadow Select the type of cache scheme to be used for this memory range The optimal and fail safe default is disabled Disabled Uncached Write Protect Cached Write Through Cache...

Page 46: ...d Disabled Uncached Write Protect Cached Write Through Cached Write Back Cached SOUTH BRIDGE CONFIGURATION South Bridge Configuration You can use this screen to select options for the South Bridge Con...

Page 47: ...permanent changes to the system configuration Select Exit Discarding Changes from the Exit menu and press Enter Discard Changes and Exit Setup Now Ok Cancel appears in the window Select Ok to discard...

Page 48: ...Chapter 2 BIOS Configuration ATXP 875P Technical Reference 38 Chassis Plans User s Notes...

Page 49: ...ry slots with the following features System Memory Features 2 6 V only 184 pin DDR SDRAM DIMMs with gold plated contacts Unbuffered single sided or double sided DIMMs with the following restriction Do...

Page 50: ...stem address space can be utilized on a system that has 2 GB of installed system memory AGP aperture set for 256 MB and the PCI cards are requesting 200 MB of system address space NOTES When ECC DIMMs...

Page 51: ...its 8 B from the memory channels If both the channels are populated with uneven memory DIMMs then the MCH defaults to virtual single channel mode The MCH behaves identically in both single channel and...

Page 52: ...o that single ROW resulting in opening and closing of accessed pages in that ROW In this example the memory configuration was DS DIMM hence FSB address bit A 19 will be used for Rank selection between...

Page 53: ...vel Configuration Characteristics Highest Dual Channel with Dynamic Mode All DIMMs matched Dual Channel without Dynamic Mode DIMMs matched from Channel A to Channel B DIMMs not matched within channels...

Page 54: ...ut Level Configuration Characteristics Highest Dual Channel with Dynamic Mode All DIMMs matched Dual Channel without Dynamic Mode DIMMs matched from Channel A to Channel B DIMMs not matched within cha...

Page 55: ...evel Configuration Characteristics Highest Dual Channel with Dynamic Mode All DIMMs matched Dual Channel without Dynamic Mode DIMMs matched from Channel A to Channel B DIMMs not matched within channel...

Page 56: ...Chapter 3 Upgrading ATXP 875P Technical Reference 46 Chassis Plans User Notes...

Page 57: ...evice support Two Serial ATA IDE connectors which support one device per connector Parallel ATA IDE Interfaces The ICH Hance Rapids Parallel ATA IDE controller has two independent bus mastering Parall...

Page 58: ...ration and two devices per channel For compatibility the underlying Serial ATA functionality is transparent to the operating system The Serial ATA controller can operate in both legacy and native mode...

Page 59: ...3D applications While based on the PCI Local Bus Specification Rev 2 2 AGP is independent of the PCI bus and is intended for exclusive use with graphical display devices AGP overcomes certain limitat...

Page 60: ...ST Display Diagnostics Miscellaneous CMOS Battery RTC with lithium battery Control Panel Connections Reset Soft Power Speaker LEDs for power and IDE CPU Socket Standard ZIF Zero Insertion Force mPGA 4...

Page 61: ...ATXP 875P Technical Reference Appendix A Technical Specifications Chassis Plans 51 Mechanical Drawing...

Page 62: ...BIOS and Buffer 640K 768K 0A0000 0BFFFF 128 KB Standard PCI ISA Video Memory 633K 640K 09E400 09FFFF 7KB BIOS Reserved 512K 633K 080000 09E3FF 121 KB Ext Conventional memory 0K 512K 000000 07FFFF 512...

Page 63: ...condary IDE channel 01F0 _ 01F7 Primary IDE channel 0278 027F LPT2 if selected 02E8 02EF COM4 default 02F8 02FF COM2 default 0376 Secondary IDE channel command port 0377 Floppy channel 2 command 0377...

Page 64: ...0 1F 03 ICH SMBus Controller 00 1F 05 ICH AC97 Audio Controller 01 00 00 AGP Card 02 01 00 Intel 82547GI LAN optional 03 02 00 PCI X expansion slot 1 03 03 00 PCI X expansion slot 2 03 04 00 LAN1 Cont...

Page 65: ...0011b PCI Interrupt Routing Map ICH Signal ID SEL PIRQA PIRQB PIRQC PIRQD PIRQE PIRQF PIRQG PIRQH PCI Slot 1 AD16 INTA INTB INTC INTD PCI Slot 2 AD17 INTB INTC INTD INTA PCI Slot 3 AD18 INTC INTD INTA...

Page 66: ...connectors are numbered from right to left when viewed from front The following rows resume the counting on the same side of pin number 1 The counting is NOT circular like Integrated Circuits legacy...

Page 67: ...OUND USB3 Table A 12 J10 Serial Port SER C Header Connector Pin Serial Port Header J10 1 DCD RS 422 485RXB opt 2 DSR 3 RX RS 422 485TXB opt 4 RTS 5 TX RS 422 485TXA opt 6 CTS 7 DTR 8 RI RS 422 485RXA...

Page 68: ...B Ethernet 1 optional 1Gbe Connector Pin USB Connector J3A 1 5V USB0 2 D USB0 3 D USB0 4 GROUND USB0 5 5V USB1 6 D USB1 7 D USB1 8 GROUND USB1 Pin Ethernet 1 optional 1Gbe Connector J3B 1 TX TX1 optio...

Page 69: ...Mouse CLK 2 Keyboard CLK 3 HDD LED 4 Keyboard Data 5 VCC 6 VCC 7 GND 8 Mouse Data 9 GND 10 Key Table A 17 J4A1 Parallel DB25 Connector Pin Parallel DB25F J4A1 1 STROBE 2 DATA BIT 0 3 DATA BIT 1 4 DATA...

Page 70: ...J1 1 GPIO24 2 GPIO25 3 GPIO27 4 GPIO37 5 GPIO38 6 GND 7 GPIO39 8 GPIO40 9 GPIO41 10 GPIO42 11 GPIO43 12 GND Table A 19 CPU Fan Rear Chassis Fan Intruder and Speaker Connector Description CPU FAN J2F1...

Page 71: ...ont Panel Header Connector Pin Front Panel Header J14 1 HDD LED Anode 2 Power LED Green Blink 3 HDD LED Cathode 4 Power LED Yellow Blink 5 Reset GND 6 Power Switch 7 Reset 8 Power Switch GND 9 5V 10 N...

Page 72: ...Appendix A Technical Specifications ATXP 875P Technical Reference 62 Chassis Plans User Notes...

Page 73: ...offers the standard FLASH BIOS When installed you will be able to update your BIOS without having to replace the EEPROM The AMIBIOS will read the new BIOS file from a floppy disk during boot and repl...

Page 74: ...t executed start memory refresh and do memory sizing in Bootblock code Do additional chipset initialization Re enable CACHE Verify that flat mode is enabled D4 Test base 512KB memory Adjust policies a...

Page 75: ...ARMD and ATAPI CDROM EB Disable ATAPI hardware Jump back to checkpoint E9 EF Read error occurred on media Jump back to checkpoint EB F0 Search for pre defined recovery file name in root directory F1...

Page 76: ...t strap processor Information C2 Set up boot strap processor for POST C5 Enumerate and set up application processors C6 Re enable cache for boot strap processor C7 Early CPU Init Exit 0A Initializes t...

Page 77: ...rors to the user and gets the user response for error 87 Execute BIOS setup if needed requested 8C Late POST initialization of chipset registers 8D Build ACPI tables if ACPI is supported 8E Program th...

Page 78: ...d controller Function 4 searches for and configures all PnP and PCI boot devices Function 5 configures all onboard peripherals that are set to an automatic configuration and configures all remaining P...

Page 79: ...mode AA System is running in APIC mode 01 02 03 04 05 Entering sleep state S1 S2 S3 S4 or S5 10 20 30 40 50 Waking from sleep state S1 S2 S3 S4 or S5 Critical Error BEEP Codes The following table desc...

Page 80: ...When AMIBIOS performs the Power On Self Test it writes diagnostic codes checkpoint codes to I O port 0080h where the POST code display is connected Please refer to Appendix B for POST codes descriptio...

Page 81: ...dvanced interrupt moderation hardware manages interrupts generated by the 82540EM controller to further improve system efficiency In addition using hardware acceleration the controller also offloads t...

Page 82: ...ther the input is above 3 V or less than 3 V The line length is limited by the allowable capacitive load of less than 2500 pF This results in a line length of approximately 20 m The maximum slope of t...

Page 83: ...it is not capable of bidirectional transfer it is still applicable and used for talker audience scenarios Electrical TIA EIA 422 ITU T V 11 is comparable to TIA EIA 485 It is limited to unidirectiona...

Page 84: ...Additionally since the signal line emits the opposite signal like the adjacent signal return line the emissions cancel each other This is true in any case for crosstalk from and to neighboring signal...

Page 85: ...tial transmission on cable lengths of up to 1200 m and at data rates of typically up to 35 Mbps requirement similar to TIA EIA 422 but tr 30 of the bit duration there are also faster devices available...

Page 86: ...hs to ground Obviously having a solid ground connection so that both receivers and drivers can talk error free is imperative The figure below shows how to make this connection and recommends adding so...

Page 87: ......

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