VC-5MC-M/C110H User's Manual
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5.3
Camera Block Diagram
The block diagram of the VC-5MC-M/C110H is shown below.
Figure 5-1 Camera Block Diagram
All controls and data processing of a camera in the VC-5MC-M/C110H are carried out in one
FPGA chip. The FPGA generally consists of a 32-bit RISC Micro-Controller and Processing &
Control logic. The Micro-Controller receives commands from the user through the Camera Link
interface and then processes them. The Processing & Control logic processes the image data
received from the CMOS image sensor and then transmits data through the Camera Link
interface. The Processing & Control logic also controls time-sensitive trigger inputs and output
signals. Furthermore, Flash and DDR3 are installed outside FPGA. The DDR3 is used for the
frame buffer to process images and the Flash stores the firmware to operate the Micro-Controller.
