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DAMC-FMC2ZUP User’s Manual

DAMC-FMC2ZUP Architecture

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Figure 2-2:

Clock Network Diagram

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Summary of Contents for DAMC-FMC2ZUP

Page 1: ...P User s Manual 1 DAMC FMC2ZUP Zynq Ultrascale MPSoC based Dual FMC FMC Carrier Board with MicroTCA 4 D1 1 support User s Manual All Rights Reserved CAEN ELS s r l Rev 1 0 April 2021 MTCA 4 MicroTCA f...

Page 2: ...DAMC FMC2ZUP User s Manual 2 This product is licensed by CAEN ELS s r l in AREA Science Park S S 14 km 163 5 34149 Basovizza TS Italy Mail info caenels com Web www caenels com...

Page 3: ...ASH PROGRAMMING 22 2 6 WHITE RABBIT SUPPORT 22 3 MODULE MANAGEMENT CONTROLLER 23 3 1 SERIAL CONSOLE 23 3 2 JTAG MULTIPLEXING 23 3 3 HPM UPDATE 24 3 4 XMODEM UPDATE 24 3 5 FPGA BOOT MODE SELECTION 24 3...

Page 4: ...DAMC FMC2ZUP User s Manual 4 Document Revisions Document Revision Date Comment Preliminary Release October 2020 Preliminary Release 1 0 April 2021 First Release...

Page 5: ...to 80 RH non condensing Altitude Up to 2000 m Pollution degree 2 Storage Temperature 10 C to 60 C Storage Humidity 5 to 90 RH non condensing CAEN ELS will repair or replace any product within the guar...

Page 6: ...to x4 con guration in this use case to accommodate non conventional backplane topologies Gigabit Ethernet port 0 is directly connected to the PS subsection of the FPGA while port 1 connects to the PL...

Page 7: ...his offers the possibility to omit a CPU boards in the MicroTCA systems The RTM interface is designed according to class D1 1 and implements the full set of 42 LVDS lines and 2 MGT links The board sup...

Page 8: ...nd USB host capability may save a CPU module Zone 3 Class D1 1 compliance with full interlock support 64 bit 4 GiB DDR4 with 2400 MT s connected to PS accessible from PL via AXI Bridge 16 bit 1 GiB DD...

Page 9: ...ere are two ordering option for the two versions of the DAMC FMC2ZUP carrier board Description Ordering Code MicroTCA 4 Zynq UltraScale FMC Carrier with XCZU11EG L2FFVC1760E DAMCFMC2ZUP1 MicroTCA 4 Zy...

Page 10: ...the board Components on side 1 top side 1 Main FPGA Zynq Ultrascale 2 FMC connector 3 FMC HPC connector 4 Secondary FPGA Spartan 7 5 DDR4 memory modules PS a PL b 6 Power Section 7 Ethernet IC 8 Main...

Page 11: ...ion 11 Components on side 2 bottom side 1 MMC 2 MLVDS transceivers 3 Flash memories for FPGA con guration a Zynq Ultrascale b Spartan 7 4 Power Management 5 Clock Section 6 eMMC memory Figure 1 2 DAMC...

Page 12: ...and 1 GbE interface on Port 0 is provided through a specialized RGMII to Ethernet 1000 baseX IC to guarantee fully compliance to the MicroTCA standard The RGMII communication is under control of the...

Page 13: ...e PCIe interface or to implement any other supported protocol restrictions may apply depending on MicroTCA system con guration Low Latency Links ports 12 to 15 As for the previous link these ports are...

Page 14: ...DAMC FMC2ZUP User s Manual DAMC FMC2ZUP Architecture 14 Figure 2 1 Block Diagram...

Page 15: ...HA 00 HA 01 and HA 17 are clock capable pins and are routed to dedicated inputs on the FPGA allowing them to access the clock resources of the PL MGT interfaces A total of 24 MGT 6 full MGT Quads are...

Page 16: ...rface are routed to the PL section of the FPGA All the signals reside on the same I O bank HA 00 HA 01 and HA 17 are clock capable pins and are routed to dedicated inputs on the FPGA giving them acces...

Page 17: ...RTM CLK1 This signal is driven by the RTM module and fed to the clock network as will be described in Section 2 2 GTP0 1_CLK_IN and GTP0 1_CLK_OUT Transceiver reference clocks from to the RTM are part...

Page 18: ...he Main FPGA and to the PLL towards the Zone3 connector The other outputs are used as reference for MGTs and to synchronize the PL section of the Main FPGA The secondary PLL listed as PS PLL in the pr...

Page 19: ...DAMC FMC2ZUP User s Manual DAMC FMC2ZUP Architecture 19 Figure 2 2 Clock Network Diagram...

Page 20: ...tage and current readouts and is responsible to bring the board to a safe condition whenever a supply voltage is out of speci cations This component also allows trimming the output voltages and it s r...

Page 21: ...GA PS JTAG Interface with all internal Controllers accessible by default refer to Xilinx UG1085 Zynq UltraScale Device TRM Chapter 39 Figure 39 1 Secondary FPGA JTAG Interface FMC and FMC connectors J...

Page 22: ...hrough IPMI instructions HPM 1 Hardware Platform Management 2 6 White Rabbit Support The board provides most of the necessary infrastructure needed to implement a White Rabbit End Point The interconne...

Page 23: ...the front panel USB connector It uses VT100 escape sequences to support convenience features like colors autocompletion and shell history To avoid flooding dumb terminals with unsupported escape sequ...

Page 24: ...HPM targets can also be updated via XMODEM over the serial USB The update has to be initiated with the xm console command 3 5 FPGA boot mode selection The ZUP boot mode can be set to JTAG first or sec...

Page 25: ...eying RTMs are compatibility checked according to the MicroTCA 4 1 standard The RTM s FRU is searched for a Zone3 Compatibility Record matching the AMC and payload power to the AMC is only enabled if...

Page 26: ...available on this interface 2 User accessible LEDs from Main FPGA PL 3 High Density microHDMI type D with proprietary pinout for White Rabbit with 2 leds 4 microSD slot Can be used to expand storage c...

Page 27: ...x based operating systems when an USB cable is connected to this interface 2 new devices will appear into the dev folder usually they are identi ed as tty devices Monitoring the output of the dmesg co...

Page 28: ...gnment of the 2 Extension Power Connectors available on the board see Figure 1 1 DAMC FMC2ZUP Top side Figure 5 1 Pin allocation of Extension Power Connectors Pins 1 3 and 5 are connected to VCC12_FMC...

Page 29: ...On the front panel it is also present a High Density microHDMI connector type D that can be used for trigger clock white rabbit purposes The block diagram of the available connections is shown in the...

Page 30: ...connections Trigger signals can be used to provide an external trigger to the Main FPGA or to send such signal from the board to another device Trigger signals on the connector are differential LVDS a...

Page 31: ...FPGA F20 FMC1 Vadj TRIGGER_1_P Main FPGA E20 FMC1 Vadj TRIGGER_0_P Main FPGA D19 FMC1 Vadj TRIGGER_0_N Main FPGA C19 FMC1 Vadj SFP_TX_P Main FPGA U6 AC coupled SFP_TX_N Main FPGA U5 AC coupled SFP_RX...

Page 32: ...1 2 Get Set JTAG multiplexing st 0 15 Get Set RTM temp sensor mask rte enable override Get Set RTM e keying policy cfu CPLD force update fru 0 n Dump FRU information bz jtag qspi qspi2 sd pjtag raw Ge...

Page 33: ...DAMC FMC2ZUP User s Manual Appendix 33 Figure 5 6 FMC connections...

Page 34: ...DAMC FMC2ZUP User s Manual Appendix 34 Figure 5 7 FMC connections...

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