DAMC-FMC2ZUP User’s Manual
Introduction
6
1.
Introduction
This chapter presents the overall characteristics and features of the DAMC-
FMC2ZUP FMC carrier board.
1.1
DAMC-FMC2ZUP Description
The DAMC-FMC2ZUP is a high-end FMC/FMC+ carrier in MicroTCA.4 form
factor based on the new family of ZYNQ Ult MPSoCs. The host FPGA is the
Xilinx ZU11EG-L2 or the ZU19EG-L2. The PS (Processing System) section offers a
quad-core ARM Cortex-A53 operating up to 1.333 GHz, a dual core ARM-R5 real-
time processor running up to 533 MHz and Mali-400 MP2 graphics up to 600 Mhz.
The board features extensive MicroTCA.4 backplane connectivity. PCI express
Gen.3 x4 link is supported on port 4-7 and can be expanded to x8 using ports 8-11 in
systems that support this mode of operation.
The card supports full multi-gigabit point-to-point link connectivity (low-
latency links) on ports 12-15. This can eventually be expanded to include ports 8-11
(PCIe is restricted to x4 configuration in this use-case) to accommodate non-
conventional backplane topologies.
Gigabit Ethernet port 0 is directly connected to the PS subsection of the FPGA
while port 1 connects to the PL (Programmable Logic) MGTs to allow
implementation of a SGMII interface over backplane.
Two transceivers from PS are connected to AMC port 2 and 3, allowing
attachment of up to two standard off-the-shelf MicroTCA SATA cards with hard
drives or SSDs.
All eight M-LVDS Timing/Trigger signals on ports 17-20 are accessible.
The four TCLK lines and the Fabric FCLKA are all connected to the internal
clock distribution network. A flexible clock scheme leveraging a 16-channel bi-
directional cross point switch allows to receive and/or drive any clock from/to the
backplane (TCLKA, TLCKB, TCLKC, TCLKD) and from/to the FMCs (bi-
directional clocks).
The board features two DDR4 interfaces, a 64-bits wide 4GB memory directly
attached to the PS and a 16-bits wide 1GB memory connected to the PL, both
memories operate by default at 2400 MT/s, with the option to increase the data-rate to
2666 MT/s for the PL when the board does not operate on low-power core voltage.
Summary of Contents for DAMC-FMC2ZUP
Page 14: ...DAMC FMC2ZUP User s Manual DAMC FMC2ZUP Architecture 14 Figure 2 1 Block Diagram...
Page 19: ...DAMC FMC2ZUP User s Manual DAMC FMC2ZUP Architecture 19 Figure 2 2 Clock Network Diagram...
Page 33: ...DAMC FMC2ZUP User s Manual Appendix 33 Figure 5 6 FMC connections...
Page 34: ...DAMC FMC2ZUP User s Manual Appendix 34 Figure 5 7 FMC connections...
