CAENels DAMC-FMC2ZUP, User Manual

Page: 17 / 34

DAMC-FMC2ZUP User’s Manual DAMC-FMC2ZUP Architecture
17
2.1.4 Zone3 Connectivity
Zone3 connectivity in accordance to recommended pinout of Class D1.1 is
achieved as follows:
•
Fixed LVDS outputs OUT0 to OUT2:
These links use specialized LVCMOS to LVDS drivers under full control of MMC
Stamp SoM (System on Module). The driving signals are provided by the CPLD
embedded on the MMC module.
•
AMC TCLK and CLK1:
These signals are driven by the clock network as will be described in Section 2.2. To
comply the unpowered/unconnected interface requirements described in the
recommendation document, a LVDS buffer is used on both signal paths. The MMC
has control over the enable signal of these buffers as required by the eKeying process.
•
RTM CLK1:
This signal is driven by the RTM module and fed to the clock network as will be
described in Section 2.2.
•
GTP0-1_CLK_IN and GTP0-1_CLK_OUT:
Transceiver reference clocks from/to the RTM are part of the clock distribution
network and described in Section 2.2.
•
GTP0 and GTP1 TX and RX pairs:
High speed transceiver lanes are routed to dedicated TX and RX interfaces on a PL
MGT Quad. This Quad is shared by the MGTs routed to the port 1 of the MicroTCA
backplane and to the Micro HDMI type D connector on the front panel.
•
LVDS I/O differential pairs:
A total of 24 LVDS pairs are available for user defined application on the Zone3
connector, these signals are routed to the Spartan 7 FPGA and from there, with a
proprietary interface, to the main FPGA. This arrangement allows to interface to a
RTM card whose logic levels are 2.5V.
•
Zone3 Management and Debug:
Presence, I2C bus and JTAG signals are routed to the MMC Stamp SoM.