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DAMC-FMC2ZUP User’s Manual DAMC-FMC2ZUP Architecture
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2.2 Clock Tree Architecture
The clock architecture is based on a bidirectional cross-point switch and 3
independent PLLs.
The cross-point switch is connected to:
•
4 Telecommunication Clock signals (TCLKA, TCLKB, TCLKC and TCLKD)
provided on standard MicroTCA backplanes
•
3 digital clocks to and from the Zone3 connector
•
the 2 bidirectional clocks of each FMC modules (CLKBIDIR2/3)
•
one of the output clocks of the White Rabbit section
•
FPGA I/O pins with dedicated access to internal clock tree resources
•
the main PLL located on the board.
The board is capable of driving and receiving clock signals from any of the 4
TCLK dedicated paths of the MicroTCA backplane and from the bidirectional clocks
of FMCs. The main PLL IC receives one input clock from the cross-point switch and
provides one of its outputs back to it. The second input of this component can be
externally provided through the Micro HDMI type D connector. Two of main PLL
output are routed to the inputs of the 2 secondary PLL, used to fed the PS on the Main
FPGA, and to the PLL towards the Zone3 connector. The other outputs are used as
reference for MGTs and to synchronize the PL section of the Main FPGA.
The secondary PLL listed as PS PLL in the previous block diagram is
responsible to provide the needed reference clocks to PS section of the Main FPGA.
Any modification in the register values of this component might impact negatively the
performances of the PS and in some cases prevent the ARM cores from booting up.
The Zone3 PLL provides the RTM related clocks and synchronization
between the secondary FPGA (Spartan 7) and Main FPGA to ensure the proper
functionality of the interconnection bus. The Fabric Clock (FCLKA) distributed by
the MCH in a MicroTCA system is connected, through a PCIe compliant jitter cleaner
IC, to a reference clock input of the MGT Quad used to implement the PCIe
connectivity on ports 4-7. Fixed frequency clock resources are connected to various
components to ensure proper operation and availability of a reference signal to the
programmable logic even before the local PLLs are accessed and configured by the
user code.
The PLLs are accessible over an I2C bus by both the MMC Stamp SoM and
Main FPGA PS.
The block diagram of the clock network is presented in the following figure: