Document type:
Title:
Revision date:
Revision:
Installation Guide (MUT)
Mod. SY1527, universal multichannel power supply system
03/12/02
3
NPO:
Filename:
Number of pages:
Page:
00103/97:1527x.MUTx/03 HWGUIDE_REV3.DOC
62
38
GEN:
Mechanical specifications:
00-type LEMO connector.
Electrical specifications:
std. NIM level or TTL level.
Function:
GENERAL STATUS indication; corresponds to the logic
combination, defined by the user, of OVC, UNV, OVV, TRIP.
4.3.3 I/O
CONNECTORS
4.3.3.1 I/O control section
All the following I/O connectors are referred to the COMMON GROUND and are
galvanically insulated up to 150 V with respect to the ground of the crate (CRATE
GROUND).
The following connectors are placed in the
I/O control
area of the front panel:
HV SYNC:
Mechanical specifications:
2-pin LEMO connectors.
Electrical specifications:
Bidirectional differential signals; RS485
standard, 1.25 MHz.
Function:
this is the synchronisation clock for the Power Supply Units
(1.25 MHz). It can work either as MASTER (relevant red LED on), i.e. the
synchronisation clock is internally generated and the HVSYNC connector
works as output, or as SLAVE, i.e. the synchronisation clock is externally
generated and send through the HV SYNC connector which works as
input.
LOCAL NET: Mechanical specifications:
2-pin LEMO connectors.
Electrical specifications:
Bidirectional differential signals.
Function:
LOCAL bus for the control of ‘non-intelligent’ systems ONLY.
This connector must not be used to connect more ‘intelligent’ SY1527
crates in daisy-chain.
CAENET:
Mechanical specifications:
00-type LEMO connectors.
Electrical specifications:
Bidirectional CAENET.
Function:
Usual H.S. CAENET interface.
TRIP IN/OUT: Mechanical specifications:
Header 5x2 flat connectors (3M, 3793-6202).
Electrical specifications:
Bidirectional differential signals. See Fig. 4.1,
p.38 for pin assignment.
Function:
four external TRIP lines to handle TRIP conditions.
Notch
TRIP IN/OUT
Pin 1
1
2
3
4
10
9
8
7
6
5
TRIP_H3
GROUND
TRIP_H2
TRIP_L3
GROUND
TRIP_L2
TRIP_H1
TRIP_H0
TRIP_L1
TRIP_L0
Fig. 4.1 – TRIP IN/OUT pin assignment