background image

1

2

3

4

5

6

7

8

A

B

C

D

8

7

6

5

4

3

2

1

D

C

B

A

BVME4000/6000

Title

Issue

Dwg No.

Drawn By

Date

Sheet

7

of 8

7

BVM00228

BVM Ltd.
Hobb Lane.
Hedge End
Southampton
SO30 0GH
(01489) 780144

Approved

Size

A2

PD1
PD2
PD3
PD4
PD5
PD6
PD7
PD8

/PSTROBE

PDATA1
PDATA2
PDATA3
PDATA4
PDATA5
PDATA6
PDATA7
PDATA8

/PACKNOW

PBUSY

/PEN
PDIR

/PEN
PDIR

PDATA1
PDATA2
PDATA3
PDATA4
PDATA5
PDATA6
PDATA7
PDATA8

/PSTROBE

/PACKNOW

PBUSY

/PBSY

PSTRB

PACK

SCLKA

SCLKB

SCLKSL1

SCLKSL0

SCLKSL1

SCLKSL0

SCLKA

SCLKB

RXCLKA
RXCLKA

RXCLKB

RXCLKB

SRXDA

STXDA

STXDB

SRXDB

STXDB

SRXDB

SRXDA

STXDA

SRTSA
SCTSA
SDTRA

SRTSB
SCTSB
SDTRB

SRTSA

SCTSA

SDTRA

SRTSB

SCTSB

SDTRB

A2
A3
A4
A5
A6

A2
A3
A4
A5
A6

A2

A3

CLK8M

GND

TXDA

RXDA

CTSA
RTSA
DTRA
GND

GND

TXDB

RXDB

CTSB
RTSB
DTRB
GND

RXDA

TXDA

CTSA

RTSA

DTRA
DTRB

RXDB

TXDB

CTSB

RTSB

+12V

+12V

+12V

/RTCCS
/SERRD
/SERWR

/SERCS
/SERRD
/SERWR

/PITCS

/CPUWE

/RTCINT

/SERACK
/SERINT

SDCDA
SDCDB

SDCDA

SDCDB

D0
D1
D2
D3
D4
D5
D6
D7

D0
D1
D2
D3
D4
D5
D6
D7

D0
D1
D2
D3
D4
D5
D6
D7

/TIMACK

/PARACK

/PARINT

/TIMINT

BAUDCLK

BAUDCLK
BAUDCLK

BAUDCLK

BAUDCLK

SERCLK

PITCLK

RQLVL1

RQLVL0

T1OUT

T1OUT

/CPURST

DCDA
DCDB

/SYSCON_A
/RRS

D0

18

D1

19

D2

20

D3

21

D4

22

D5

23

D6

24

D7

25

CE

1

RD

2

WR

3

A0

4

A1

5

A2

6

A3

7

A4

8

OSC_OUT

13

OSC_IN

12

VBB

11

PFAIL

27

INTR

17

MFO

16

T1

10

TCK

26

G0

15

G1

9

IC14

DP8570AV

XL1
32.768KHz

D0

48

D1

49

D2

50

D3

51

D4

52

D5

1

D6

2

D7

3

CE

45

RESET

43

WR

47

RS1

32

RS2

31

RS3

30

RS4

29

RS5

28

PA0

4

PA1

5

PA2

6

PA3

7

PA4

9

PA5

10

PA6

11

PA7

12

PB0

18

PB2

22

PB3

23

PB4

24

PB5

25

PB1

19

PB6

26

PB7

27

H1

14

H2

15

H3

16

H4

17

PC0

34

PC1

35

PC4

38

TOUT

37

PIRQ

39

DTACK

46

BCLK

44

TIACK

41

PIACK

40

TIN

36

IC15

MC68230FN

A1

2

A2

3

A3

4

A4

5

A5

6

A6

7

A7

8

A8

9

G

19

DIR

1

B1

18

B2

17

B3

16

B4

15

B5

14

B6

13

B7

12

B8

11

IC16

74ABT245

3

4

IC17B

74F14

1

2

IC17A

74F14

5

6

IC17C

74F14

D0

1

D1

2

D2

44

D3

3

D4

43

D5

4

D6

42

D7

5

CE

38

INT

6

IEI

8

IEO

7

CLK

23

RXDA

14

RTXCA

13

TXDA

16

TRXCA

15

SYNCA

12

W/REQA

11

RTSA

20

CTSA

21

DTRA

19

DCDA

22

RXDB

31

TXDB

29

RTXCB

32

SYNCB

33

W/REQB

34

RTSB

26

CTSB

25

DTRB

27

DCDB

24

RD

41

WR

40

A/B

39

D/C

37

INTACK

9

TRXCB

30

IC18

Z8530V

C+

1

C-

2

T1IN

8

T2IN

7

R1OUT

9

R2OUT

6

V+

14

T1OUT

11

T2OUT

4

R1IN

10

R2IN

5

V-

3

IC19

MAX231

1

2

+

C6
4u7

1

2

+ C7

4u7

C+

1

C-

2

T1IN

8

T2IN

7

R1OUT

9

R2OUT

6

V+

14

T1OUT

11

T2OUT

4

R1IN

10

R2IN

5

V-

3

IC20

MAX231

1

2

+

C8
4u7

1

2

+ C9

4u7

1

2

+

C10
4u7

1

2

+ C11

4u7

C+

1

C-

2

T1IN

8

T2IN

7

R1OUT

9

R2OUT

6

V+

14

T1OUT

11

T2OUT

4

R1IN

10

R2IN

5

V-

3

IC21

MAX231

1C0

6

1C1

5

1C2

4

1C3

3

2C0

10

2C1

11

2C2

12

2C3

13

A

14

B

2

1G

1

2G

15

1Y

7

2Y

9

IC22

74F153

Vcc

R25
4K7

Vcc

R26
4K7

Vcc

R27
4K7

1

2

3

4

5

6

7

8

9

10

11

12

13

14

JP1

HDR7X2

1

2

3

4

5

6

7

8

9

10

11

12

13

14

JP2

HDR7X2

C5
10pF

C4
47pF

CLK

5

NC

1

XM3

XM8-7.3728MHz

/PITACK

WDOG

Vcc

R106
470R

Vcc

R107
470R

SCLKOUTA

SCLKOUTB

Vcc

R113

4K7

GND

GND

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

JP3

R102
10K

+12V

R103
10K

+12V

+12V

R104
10K

R105
10K

/RTCCS

/PITCS

/RTCINT

/SERACK

/SERINT

/SERCS
/SERRD
/SERWR

/IPL2
/IPL1
/IPL0

/AVEC

VMEA3
VMEA2
VMEA1

VMEAM2
VMEAM1
VMEAM0

/VMEDS0

/VMEIAK
/VIAKIN
/VIAKOUT

/TIMACK
/PARACK

/TIMINT
/PARINT

D6
D5
D4
D3
D2
D1
D0

VMEMST
/VMESLV

A2
A1

TT1
TT0

/IPENC2
/IPENC1
/IPENC0

CPUCLK

/IPAKIN

/CSVIAK

ABORT

ABORT

/TS
/TA

/MIRQ

SERCLK

CPUCLK1

CPUCLK

/CONFRD

GND

D3
D2
D1
D0

CSW3
CSW2
CSW1
CSW0

/VILVL2
/VILVL1
/VILVL0

/ETHINT
/SCSINT

PITCLK

/PITACK

/ROMOE
/ROMLE

ROMA1

/CONFRD

CS3
CS2
CS1
CS0

/TS
/TA

/CPUWE

TM2
TM1
TM0

TT1
TT0

SIZ1
SIZ0
A1
A0

TM2
TM1
TM0

/SERACK

/TIMACK
/PARACK

/BR040

/BG040

/BRVME

/BBSY

/LOCK
/LOCKE

/BGSCSI

/BGVME

HOLDA

/ETHBOFF
/BS16

/ETHBE3
/ETHBE2
/ETHBE1
/ETHBE0

/ETHADS

/BRSCSI
BRENET

/IPLWE
/IPIFWE
/VSLVWE

/IPLWE

/SCSICS

/ETHERR

/VMEINT

/VSLVIAK

/Q_TIP

/INVA1

/CPURST

/ETHPORT
/ETHCA

/ETHBRQ

/LOCDET

ETHWE

ETHRST

/TEA

D7

/TEA

/RAMOE

/RAMWE

A3

9

8

IC17D

74F14

1

2

SW1

C12
220pF

A1

3

A2

4

A3

5

A4

6

GAB

1

GBA

13

B1

11

B2

10

B3

9

B4

8

IC63

74F243

1
2
3
4

8
7
6
5

SW3

Vcc

R31
4K7

1

2

LK1

CPUCLK

13

RESET

18

TS

6

TA

83

TEA

38

CPUWE

33

TT1

69

TT0

73

TM2

72

TM1

20

TM0

36

SIZ1

76

SIZ0

75

A1

74

A0

48

CS3

34

CS2

23

CS1

22

CS0

4

TIMIAK

61

PARIAK

60

SERIAK

59

BBSY

7

LOCK

46

LOCKE

45

BR040

54

BRSCSI

55

BRENET

35

BRVME

47

TIP

57

PITCLK

50

PITCS

71

PITACK

58

ROMOE

97

ROMLE

98

ROMA1

82

RAMWE

100

RAMOE

99

SERCLK

96

SERCS

86

SERRD

87

SERWR

88

RTCCS

81

BGG040

56

BGSCSI

19

BGVME

26

ETHBRQ

49

HOLDA

8

ETHERR

11

BOFF

12

BS16

70

ETHADS

43

ETHBE3

24

ETHBE2

25

ETHBE1

32

ETHBE0

31

ETHWE

44

ETHRST

84

ETHPORT

85

ETHCA

9

IPLWE

37

IPIFWE

10

VSLVWE

94

CONFRD

95

SCSICS

93

MI

63

ETHMST

62

TCK

28

TMS

27

TDI

3

TDO

78

TRST

77

ENABLE

53

CSVIACK

68

ROMWE

21

IC59

MACH446-PERIPH

CPUCLK

18

RESET

88

IPENC2

87

IPENC1

86

IPENC0

85

ABORT

69

RTCINT

68

TIMINT

54

PARINT

63

SERINT

35

LOCDET

62

ETHINT

61

SCSINT

60

MEMINT

59

TS

58

TA

56

TEA

55

TT1

26

TT0

25

TM2

34

TM1

10

TM0

8

LA3

24

LA2

98

LA1

32

VMEMST

12

VMESLV

9

INVA1

46

REGCS

11

D7

96

D6

93

D5

48

D4

100

D3

95

D2

94

D1

49

D0

31

IPL2

36

IPL1

37

IPL0

38

VIRQ7

84

VIRQ6

82

VIRQ5

81

VIRQ4

73

VIRQ3

72

VIRQ2

71

VIRQ1

70

AVEC

76

VMEACK

75

IPACK

44

TIMACK

74

PARACK

43

SERACK

50

VIAK

21

VIAKIN

47

VIAKOUT

6

VDS0

45

VA3

20

VA2

19

VA1

33

VMEAM2

22

VMEAM1

83

VMEAM0

23

VSLVIAK

7

VMEINT

99

VILVL2

97

VILVL1

57

VILVL0

5

ETHERR

13

ACFAIL

4

TCK

28

TMS

27

TDI

3

TDO

78

TRST

77

ENABLE

53

IC42

MACH446-IPL

Vcc

R40
10K

Vcc

R41
10K

Vcc

R42
10K

Vcc

R43
10K

/CPURST

/BBSY

TT0

TT1

TM0

TM1

TM2

/ETHMST

/MI

/ACFAIL

/ETHERR

/MIRQ

/CSVIAK

VBATT

/L_PFAIL

/ROMWE

CPUCLK1

/CPURST

/TS
/TA
/TEA

/CPUWE
TT1
TT0
TM2
TM1
TM0

SIZ1
SIZ0

CS3
CS2
CS1
CS0

/TIMACK
/PARACK
/SERACK

/LOCK
/LOCKE

/BRVME

/CSVIAK

/VSLVWE

/IPIFWE

/ETHMST

/BGVME

/Q_TIP

D[0..31]

A[0..31]

GND

RXCLKA

RXCLKB

A[0..31]

TCK
TMS
TDA

/TRST
/ENABLE

TDB

TCK
TMS
TDD

/TRST
/ENABLE

TDE

/IPAKIN

VIRQ1

VIRQ2

VIRQ3

VIRQ4

VIRQ5

VIRQ6

VIRQ7

/VIAKIN

/VMEDS0

/IPENC2
/IPENC1
/IPENC0

/LOCDET

VMEMST
/VMESLV
/INVA1

/VIAKOUT

VMEAM2
VMEAM1
VMEAM0

/VSLVIAK

/VILVL2
/VILVL1
/VILVL0

/VMEINT

VCC

CLK8M

SCLKOUTA

/RRS

RQLVL0
RQLVL1

/PACKNOW

PBUSY

/PSTROBE

PDATA[1..8]

PDATA[1..8]

TXDA
RTSA

RXDA
CTSA

DTRA
DTRB

DCDA
DCDB

TXDB
RTSB

RXDB
CTSB

/ACFAIL

/VMEIAK

VMEA1

VMEA2

VMEA3

SCLKOUTB

A0

1

A1

2

A2

3

WP

7

SCL

6

SDA

5

IC51

24CXX

GND

SCL
SDA

SDA
SCL

D[0..31]

10 December 1998

S J Bush

/SYSCON_A

VCC

Vcc

R90
10K

Vcc

R91
10K

Vcc

R94

4K7

Summary of Contents for BVME4000

Page 1: ...p www bvmltd co uk Board Revision F Manual Revision I 21 February 2001 This material contains information of proprietary interest to BVM Ltd It has been supplied in confidence and the recipient by acc...

Page 2: ...This page is intentionally left blank...

Page 3: ...is provided as Copyright BVM Ltd is proprietary and confidential property of BVM Ltd and each single copy is given on the agreed understanding that it is licensed for use on product combinations supp...

Page 4: ...option Damage may result if users attempt to remove or fit memory modules incorrectly Do not fit remove the 68040 68060 device to from the BVME4000 6000 Special tools are required to fit and remove th...

Page 5: ...VMEbus Interrupt Handler 8 3 11 2 Internal Interrupts 8 3 11 3 VMEbus Interrupter 8 3 12 VMEbus System Controller Functions 9 3 13 Power Supply Monitor Watchdog 9 3 14 Local Bus Monitor 9 3 15 Config...

Page 6: ...rotection Fuses 24 7 Programming 25 7 1 Address Map 25 7 1 1 I O Address Map 26 7 2 Memory Module 26 7 3 VMEbus Master Access 27 7 3 1 A16 D16 D08EO 27 7 3 2 A16 D32 27 7 3 3 A24 D16 D08EO 27 7 3 4 A2...

Page 7: ...O A16 Accesses 46 7 10 4 Controlling The Window Size 46 7 10 5 Local Address Generation 46 7 10 6 Address Control Registers 47 7 10 6 1 A32VBA A32 VMEbus Base Address Register 47 7 10 6 2 A32MSK A32 V...

Page 8: ...Programmers Guide 60 A 5 DP8570A Data Sheet 60 A 6 Z85230 User s Manual 60 A 7 MC68230 Data Sheet 60 A 8 VMEbus Specification 60 A 9 RS422 485 Interface Module User s Manual 60 A 10 AM29F040 Data Book...

Page 9: ...ion Disable Location 16 Figure 13 LK18 19 CPU 5 3 3V Selection Location 16 Figure 14 LK21 SRAM Backup Selection Location 17 Figure 15 LK22 VMEbus System Controller Enable Location 17 Figure 16 Configu...

Page 10: ...viii This page is intentionally left blank...

Page 11: ...b SRAM Other versions of the BVME4000 are available to special order where any of the VMEbus I F ETHERNET SCSI IP I F may be omitted or 512Kb SRAM fitted Contact your supplier for details 1 3 BVME6000...

Page 12: ...2 1 Board Layout STATUS LEDs VMEbus P1 CONN ABORT RESET SERIAL CH B SERIAL CH A IP I O CONN CHEAPER PRINTER CONN NET LOW PROM HIGH PROM MEMORY MODULE INTERFACE 2 X 50 WAY VMEbus P2 CONN 68040 or 6806...

Page 13: ...6 bit IP Compatible Sites Double height 32 bit access supported Expansion Connector allowing 4 IP Compatible Site daughter board 8MHz 32MHz and proprietary high speed Source Synchronous Modes supporte...

Page 14: ...troller 50 way Direct Connector EPROM 2Mb 16 Bit Wide Serial Buffers 14 way Connector JP2 14 way Connector JP1 P2 Serial SRAM 512Kb 2Mb 32 Bit Wide Memory Module R T C 2 x Timers IP Interface IP A IP...

Page 15: ...M memory modules allowing use of memory modules which currently include 8 to 48Mbytes DRAM 5 3 3 3 access at 33MHz bus clock 16 to 512Mbytes DRAM 4 1 1 1 read 3 2 2 2 write at 25 33MHz bus clock 16Mby...

Page 16: ...he SCSI interface further minimising processor overhead The SCSI interface is connected to a dedicated 50 way connector and is also available via the P2 connector 3 8 Ethernet Interface An Ethernet In...

Page 17: ...hange Both schemes use FAIR requesting ensuring each master has an equal chance of obtaining the bus Digital bus busy filtering and arbitration interleaving is used to ensure premium arbitration perfo...

Page 18: ...PU 3 11 2 Internal Interrupts Internal CPU interrupts are generated from a variety of sources as detailed in the table below Source Level Type VMEIRQ7 1 IRQ7 1 Vectored ACFAIL 7 Auto ABORT 7 Auto 8570...

Page 19: ...sor watchdog capability controlled via the Board Control Register If enabled the processor will be reset if the software fails to maintain pulses to the watchdog circuit 3 14 Local Bus Monitor All bus...

Page 20: ...l cables to JP1 and or JP2 if not using the P2 connections 8 If using Cheapernet connect the Cheapernet BNC T connector to the BVME4000 6000 BNC connector or if using the optional 10BaseT connect the...

Page 21: ...0 1 L 1 2 LK13 IC 2 XM1 INTERRUPT CONTROLLER INDUSTRY PACK LK21 LK22 3V 5V ABORT RESET CHEAPERNET CONFIG SWITCH IP B CONNECTOR IP A CONNECTOR LEDS SERIAL B SERIAL A LK15 LK14 DISK POWER CONNECTOR LK2...

Page 22: ...nd are not available for user s 5 2 1 LK1 Abort Switch Enable Figure 4 LK1 Abort Switch Enable Location Fitting this link enables the ABORT switch to generate interrupts LK1 Function 1 2 Fitted ABORT...

Page 23: ...bus 1 2 Omitted NO VMEbus RESET from BVME4000 6000 5 2 4 LK4 VMEbus Reset In Enable Figure 7 LK4 VMEbus Reset In Enable Location This link allows the BVME4000 6000 to be reset from the VMEbus RESET si...

Page 24: ...MC68040 68060 CACHES ENABLED 5 2 6 LK6 Cheapernet Heart Beat Enable Figure 9 LK6 Cheapernet Heart Beat Enable Location This link allows the CHEAPERNET Heartbeat function to be enabled LK6 Function 1...

Page 25: ...elect Location These links selects the size of EPROM in the IC44 45 32 pin EPROM sockets A 27C512 28 pin EPROM should be fitted to the lower 28 pins of the socket pins 1 2 31 32 unused LK10 LK11 LK12...

Page 26: ...NO SCSI bus termination on BVME4000 6000 5 2 10 LK18 19 CPU 5 3 3V Selection Figure 13 LK18 19 CPU 5 3 3V Selection Location These are factory set links when a 68040 series CPU is fitted 5V is select...

Page 27: ...his link forces the BVME4000 6000 to be the VMEbus System Controller so the BVME4000 6000 performs as the VMEbus arbiter drives VMEbus SYSCLK and VMEbus BCLR The normal selection for this function is...

Page 28: ...t 0 in the BVME4000 6000 Configuration Switch Register refer to 7 11 2 Configuration Switch Register on page 49 5 3 Indicators 5 3 1 Green LED RUNNING The GREEN RUNNING LED indicates that the BVME4000...

Page 29: ...ce Module on page 60 section of this manual 6 2 JP3 Parallel Port Connections JP3 carries the parallel port signals and the layout is designed to connect directly to a standard 36 way connector as sho...

Page 30: ...piece If the BVME4000 6000 is to be removed from the network this is simply accomplished by disconnecting the BVME4000 6000 BNC connector JP4 from the T piece leaving the T piece connected to the cab...

Page 31: ...ed with many mass terminated connectors Each type of connector has its own intrinsic pin numbering system Systems integrators or users making their own cables must be certain which pin corresponds to...

Page 32: ...is is for factory use only to program the internal BVME4000 6000 logic devices Figure 23 JP8 JTAG Connector 6 8 J1 SCSI Connections J1 carries the SCSI interface signals The connector pinout allows a...

Page 33: ...ins The centre row Row b carries VMEbus 32 bit extension signals The other two rows carry BVME4000 6000 specific I O connections P2 Connection Row a Row c 1 TxDA RxDA 2 RTSA CTSA 3 DTRA DCDA 4 SCLKOUT...

Page 34: ...eir functions positions rating and type Location see below Function Rating Type LittleFuse F1 SCSI TERM PWR 1 5A ALF II 42901 5 F2 ETHERNET 9V 200mA ALF II 429 200 F3 J14 5V 2A ALF II 429002 F4 J14 12...

Page 35: ...8FFFFFF EPROM 16Mb 2Mb valid D16 non cached serial 4 5 F9000000 F9FFFFFF SRAM alternate 16Mb 2Mb valid D32 non cached serial 3 5 FA000000 FCFFFFFF Reserved 48Mb FD000000 FDFFFFFF VMEbus A24 D32 16Mb D...

Page 36: ...ules are available in various configurations DRAM SRAM FLASH and sizes and access speeds Refer to the relevant Memory Module documentation detailed in the Appendix A Data Sheet Manual References on pa...

Page 37: ...dress Modifier AM codes are generated CPU Supervisor Data Access 2D CPU User Data Access 29 7 3 2 A16 D32 Base Address FFEF0000 Size 64Kbyte Accesses to this area perform a Short I O access to VMEbus...

Page 38: ...he following Address Modifier AM codes are generated CPU Supervisor Program Access 0E Data Access 0D CPU User Program Access 0A Data Access 09 7 3 6 A32 D32 Base Address Immediately above the Memory M...

Page 39: ...fer to 7 10 VMEbus Slave Access Controller on page 45 for RAMLO setting 7 5 EPROM Base Address E8000000 or F8000000 Size 2Mbyte The BVME4000 6000 provides 2 x 32 Pin EPROM JEDEC compatible sockets tha...

Page 40: ...s for SCSI data transfers Note that the 53C710 is configured for Big Endian Mode This can affect addressing in fairly subtle ways For full programming details refer to the 53C710 documentation detaile...

Page 41: ...W DSA Data Structure Address FF000014 B R CTEST3 Chip Test 3 FF000015 B R CTEST2 Chip Test 2 FF000016 B R CTEST1 Chip Test 1 FF000017 B R W CTEST0 Chip Test 0 FF000018 B R W CTEST7 Chip Test 7 FF00001...

Page 42: ...erminators are active when LK13 is omitted When LK13 is fitted then the BVME4000 6000 terminators are completely disabled and provide no load to the SCSI bus The BVME4000 6000 drives TERMPWR and uses...

Page 43: ...er to the 82596CA documentation detailed in the A 3 82596CA on page 60 section of this manual Although the CPU and the 82596CA do not generally communicate directly there is a virtual register that th...

Page 44: ...ust be set up as follows Bit 6 Must be set INT Bit 5 Must be clear active high interrupt LOCK Bit 4 LOCKed cycles are supported on the BVME4000 6000 It is recommended that the LOCK function be enabled...

Page 45: ...see 7 8 4 1 VMEIRQ Enable Register on page 36 VMEbus ACFAIL 7 Auto vectored Where multiple sources are generating interrupts on the same level the acknowledge cycle is prioritised as follows Highest P...

Page 46: ...VIEN4 VIEN3 VIEN2 VIEN1 ACFEN FF200007 VMEIRQ Vector VEC7 VEC6 VEC5 VEC4 VEC3 VEC2 VEC1 0 VMEIRQ Level Rsrvd Rsrvd Rsrvd Rsrvd VLVL2 VLVL1 VLVL0 1 FF20000B LOCIRQ Enable Rsrvd Rsrvd Rsrvd Rsrvd Rsrvd...

Page 47: ...us Slave Operation After RESET this bit is CLEAR i e location monitor interrupts disabled This bit is used to clear the Location Monitor Interrupt during interrupt service routines The interrupt is cl...

Page 48: ...n be used to determine that the ACFAIL signal was the source of an Auto vector level 7 interrupt Bit 1 ETHERR Ethernet ERROR Interrupt This bit indicates that a 82596CA Ethernet Controller BUS ERROR h...

Page 49: ...ppendix D IP Expansion Interface Pinout on page 67 for details The BVME4000 6000 contains all the state machine and multiplexing logic thus minimising daughter board circuitry requirements The interfa...

Page 50: ...used to take the double size IP Thus A26 to A0 are used by the IP s or IP Interface for memory space decoding as shown below Address Range A 26 23 Size IP Selected IP A 22 A1 E0000000 E07FFFFF F00000...

Page 51: ...027F 0010 0 128 byte D16 IP C I O A6 A1 FF800280 FF8002FF 0010 1 128 byte D16 IP C ID A6 A1 FF800300 FF80037F 0011 0 128 byte D16 IP D I O A6 A1 FF800380 FF8003FF 0011 1 128 byte D16 IP D ID A6 A1 FF8...

Page 52: ...ry code written selects the corresponding interrupt level e g 101 selects level 5 When set to 000 no interrupt can be generated After RESET these bits are CLEAR i e interrupt generation disabled 7 9 6...

Page 53: ...AR IP B is clocked at 8MHz or CPU Clock divided by four depending on the setting of SYNCX bit of the IP SYNCB Clock Select Register When SET the IP expansion interface is clocked at 32MHz or CPU Clock...

Page 54: ...ck frequency or CPU clock divided by 4 again dependent on the CLKB bit After RESET this bit is CLEAR i e 8 32MHz clock selected Bit 0 SYNCA IP A SYNC Clock Select When CLEAR IP A is clocked at 8 or 32...

Page 55: ...00C80000 The address decoding for A24 and A32 accesses are separate from each other There are two decoders one for A24 and one for A32 They both work by comparing the most significant byte of the addr...

Page 56: ...A32 Address Space Window Size 00 64Kb 16Mb 01 128kb 32Mb 03 256kb 64Mb 07 512Kb 128Mb 0F 1024Kb 256Mb 1F 2048Kb 512Mb 3F 4096Kb 1024Mb 7F 8192Kb 2048Mb FF 16384Kb 4096Mb 7 10 5 Local Address Generatio...

Page 57: ...en the corresponding address line is ignored Thus the contents of this register control the size of the window decoded by the BVME4000 6000 refer to 7 10 4 Controlling The Window Size on page 46 for m...

Page 58: ...e accesses are snooped by the CPU so that the CPU will sink and source dirty data refer to Appendix B CPU Cache Coherency and Bus Snooping on page 62 for a discussion on snooping and cache coherency B...

Page 59: ...tion Switch Register 7 11 1 Configuration Switch Layout Figure 27 Configuration Switch Layout 7 11 2 Configuration Switch Register Address Register D7 D6 D5 D4 D3 D2 D1 D0 FF500003 CONFSW Rsrvd Rsrvd...

Page 60: ...ware Specific Considerations INTR pin Configuration The INTR pin is fed to the Interrupt Controller refer to 7 8 Interrupt Controller on page 35 for more details It must be programmed as an active low...

Page 61: ...t Mode Timer 1 Control FF90000F RAM Interrupt Control 0 Periodic Flag FF900013 RAM Interrupt Control 1 Interrupt Routing FF900017 RAM 1 100 Second Counter FF90001B RAM Seconds Clock Counter FF90001F R...

Page 62: ...8 bit wide transceiver ALL the bits must be programmed to be in the same direction all inputs or all outputs The direction programmed must match that of the transceiver set up via port C 7 13 3 Port...

Page 63: ...the EEPROM The bit sets the data to the EEPROM in output mode and reflects the data from the EEPROM in input mode For full programming details refer to the NM24C02 documentation detailed in the A 11 N...

Page 64: ...n is connected to the Interrupt Controller s PARIACK line Bit 5 PIRQ Parallel Port Interrupt Request This output drives the 68230 Parallel Interrupt input to the Interrupt Controller refer to 7 8 Inte...

Page 65: ...FA0000B Port A Data Direction Register R W Yes No FFA0000F Port B Data Direction Register R W Yes No FFA00013 Port C Data Direction Register R W Yes No FFA00017 Port Interrupt Vector Register R W Yes...

Page 66: ...lexer controlled by the SCLKA bit of the BOARD CONTROL REGISTER Refer to 7 13 Parallel Port Timer on page 52 for more details of this register The clock source can be selected between an onboard 7 372...

Page 67: ...nnel These are generally accessed as a two step procedure First the register to be accessed is written to the Control Register then the next access to the Control Register accesses the referenced Read...

Page 68: ...pin CPU PROM sockets 16 bit wide accept 512Kbit to 8Mbit EPROM s 4Mbit FLASH 90ns 25MHz bus 120ns 33MHz bus 512K 2Mbytes CMOS SRAM 32 bit wide battery backed up to 7 days or 2 5 years 32 bit wide memo...

Page 69: ...STEM CONTROLLER enable CPU cache inhibit Cheapernet Heartbeat enable Cheapernet Ethernet select PROM type SCSI Termination select SRAM backup source select PROGRAM VMEbus SYSTEM CONTROLLER functions V...

Page 70: ...r 296853 001 INTEL 82596CA HIGH PERFORMANCE 32 BIT LOCAL AREA NETWORK COPROCESSOR DATA SHEET July 1992 INTEL order number 290218 005 A 4 53C710 Data Manual Programmers Guide NCR53C710 53C710 1 SCSI I...

Page 71: ...391 A 13 MEM400 Memory Module User s Manual MEM400 16Mbytes DRAM 4 8 Mbytes FLASH MEMORY MODULE User s Manual BVM part number 454 61400 A 14 MEM480 Memory Module User s Guide MEM480 16 32 48Mbytes DRA...

Page 72: ...till present and can be used for this function although the strategy needs to be slightly different The 68040 s Transparent Translation Registers contain an address and mask field to allow definition...

Page 73: ...the processor may not know that data in it s internal caches is now invalid This problem can be approached in a number ways 1 Normally main system memory resides on the BVME4000 and the 68040 can use...

Page 74: ...for this function although the strategy needs to be slightly different The 68060 s Transparent Translation Registers contain an address and mask field to allow definition of an address range to be us...

Page 75: ...em memory resides on the BVME6000 and the 68060 can use bus snooping to monitor accesses to the memory by any of the other bus masters The bus snooping must be enabled by programming the relevant bus...

Page 76: ...27 GND Ground 27 D26 28 A4 28 MERR Module Error 28 D27 29 A3 29 N C No Connect 29 D28 30 A2 30 GND Ground 30 D29 31 A1 31 5VSB 5V Standby Power 31 D30 32 A0 32 12V 12 Volt Power 32 D31 NOTES This all...

Page 77: ...MEM 21 D0 D1 22 D2 D3 23 D4 D5 24 D6 D7 25 D8 D9 26 D10 D11 27 D12 D13 28 D14 D15 29 A3 A4 30 A1 A2 31 ACKA ACKB 32 GND GND NOTES This allows connection to a BVM IP Expansion Daughter Board e g EXP100...

Page 78: ...ME6000 25 C 50 C 70 C 50MHz MC68EC LC060 No Heatsink No Airflow No Heatsink No Airflow No Heatsink 0 5m s Airflow 66MHz MC68EC LC060 No Heatsink No Airflow No Heatsink 0 5m s Airflow No Heatsink 1 0m...

Page 79: ...t Diagrams NOTE Circuit diagrams are provided here for customer reference only This information was current at the time this User Manual was last revised This information is not necessarily current or...

Page 80: ...erface Takes CPUCLK1 SCSI scsi sch This sheet contains SCSI Interface Takes CPUCLK1 Industry Pack Interface ip sch This sheet contains Industry Pack Interface IP Connectors EXP100 Connector Takes CPUC...

Page 81: ...27 C1 A26 E2 A25 F3 A24 D1 A23 G3 A22 E1 A21 F1 A20 G1 A19 J2 A18 H1 A17 J1 A16 K2 A15 K1 A14 L1 A13 M1 A12 N1 A11 N3 A10 P1 A9 F16 A8 E18 A7 F18 A6 G16 A5 G18 A4 H18 A3 J18 A2 J17 A1 K18 A0 L18 D31 D...

Page 82: ...51 D28 50 D27 48 D26 47 D25 46 D24 43 D23 42 D22 41 D21 40 D20 39 D19 38 D18 37 D17 36 D16 35 D15 32 D14 31 D13 30 D12 29 D11 28 D10 27 D9 26 D8 25 D7 21 D6 20 D5 19 D4 18 D3 17 D2 16 D1 15 D0 14 TXD...

Page 83: ...D7 76 D6 77 D5 78 D4 80 D3 81 D2 83 D1 84 D0 85 SD0 131 SD1 130 SD2 129 SD3 127 SD4 126 SD5 125 SD6 124 SD7 122 SDP 121 SATN 120 SBSY 119 SACK 117 SRST 116 SMSG 115 SSEL 114 SCD 112 SREQ 111 SIO 110 S...

Page 84: ...T 26 IPDS1 57 IPDS0 87 MEMSELA 7 IOSELA 11 IDSELA 10 INTSELA 25 MEMSELB 9 IOSELB 5 IDSELB 12 INTSELB 20 ACKA 49 ACKDA 47 ACKB 46 ACKDB 45 IPENC2 6 IPENC1 19 IPENC0 22 IPD32 48 TA 74 TIP 43 TCK 28 TMS...

Page 85: ...A2 3 A3 4 A4 5 A5 6 A6 7 A7 8 A8 9 GBA 19 GAB 1 B1 18 B2 17 B3 16 B4 15 B5 14 B6 13 B7 12 B8 11 IC54 74F623 A1 2 A2 3 A3 4 A4 5 A5 6 A6 7 A7 8 A8 9 GBA 19 GAB 1 B1 18 B2 17 B3 16 B4 15 B5 14 B6 13 B7...

Page 86: ...RINT SERCS SERRD SERWR IPL2 IPL1 IPL0 AVEC VMEA3 VMEA2 VMEA1 VMEAM2 VMEAM1 VMEAM0 VMEDS0 VMEIAK VIAKIN VIAKOUT TIMACK PARACK TIMINT PARINT D6 D5 D4 D3 D2 D1 D0 VMEMST VMESLV A2 A1 TT1 TT0 IPENC2 IPENC...

Page 87: ...1 12 5 MHz or 16 67MHz Vcc R45 4K7 Vcc R46 4K7 VRSTOUT CLK_X_2 CPUCLK CPUCLK1 CPUCLK2 CPUCLK3 CLKEN R56 330R R57 270K R58 47R R59 47R C71 0 1u C72 0 1u C73 10u VCC GND VCC 1 2 C62 470u GND GND GND D11...

Reviews: