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BVME4000/6000
Copyright
1993,1995,1998,2001 BVM Ltd.
Note that instruction caching only functions in write-through mode, not copy-back mode, as no writes
occur to the instruction address space. To use write-through caching in place of copyback, the "$20"
should be replaced by a "$00" in the above values for DTT1.
The DTT1 and ITT1 values could be changed to introduce a third region of write-through caching in
addition to copy-back caching as follows for the 68EC040:
DTT1 = $000FC020, ITT1 = $000FC000
Now the on-board RAM is defined as copy-back caching from $00000000 to $0FFFFFFF and the
region from $10000000 to $EFFFFFFF is defined as write-through caching (the 68EC040's default). A
similar mechanism may be used via the page descriptors when the MMU is used in the 68040 or
68LC040.
It is useful to have different regions defined for the same address space, because as the BVME4000
dual-maps some of the address space, it can be accessed in different caching modes. If the above
scheme was adopted, then the VMEbus A24 space could be accessed at address $EE000000 as
write-through cached, and at address $FE000000 as cache-inhibited bus-serialised access.
The BVME4000 has three separate blocks capable of bus mastership (DMA) other than the processor
itself: the Ethernet Controller, SCSI Controller and the VMEbus Slave Interface. When any of these
bus masters transfer data directly into a memory region (DMA), cache coherency problems can occur,
as the processor may not know that data in it's internal caches is now invalid.
This problem can be approached in a number ways:
1.
Normally main system memory resides on the BVME4000, and the 68040 can use "bus-
snooping" to monitor accesses to the memory by any of the other bus masters. The bus-
snooping must be enabled by programming the relevant bus-snoop enable bit(s) for the bus
master in question. For the Ethernet Controller and VMEbus Slave Interface, there is a
SNOOP ENABLE bit - refer to "7.10 VMEbus Slave Access Controller (on page 45)" for more
details. For the SCSI Controller, there are SNOOP MODE bits in it's register set - refer to the
53C710 documentation detailed in the "A.4 53C710 Data Manual & Programmers Guide (on
page 60)" section of this manual.
2.
The 68040's internal caches can be "flushed" if it is known that their data may be invalid (e.g.
when an interrupt occurs after a DMA operation). It may also be necessary to do a "cache
push" if copyback caching is in use. This can be very wasteful, as data not involved in the
transfers at all will also be purged from the caches.
3.
Non-cached regions can be used to access the memory. For example, the Ethernet Controller
can be set-up to DMA into a separate buffer region (e.g. the SRAM), which is accessed via a
non-cached address. In this case, bus-snooping is not required, but the data, once DMAed
into memory, is not subject to the advantages of caching. This does also have a potential
performance advantage, as there is a timing overhead involved in bus-snooping by the 68040
processor.
Other schemes may be determined by the user, or a combination of the above may be used in
conjunction.
