BVME4000/6000
26
Copyright
1993,1995,1998,2001 BVM Ltd.
7.1.1
I/O Address Map
Address Range
Device
Size
Width
FF000000 - FF0FFFFF
SCSI Controller
1Mb
D32
FF100000 - FF1FFFFF
Ethernet Controller (LANC)
1Mb
D32
FF200000 - FF2FFFFF
Interrupt Control
1Mb
D8(OLW)
FF300000 - FF3FFFFF
IP Control
1Mb
D8(OLW)
FF400000 - FF4FFFFF
VME Slave Access Control
1Mb
D8(OLW)
FF500000 - FF5FFFFF
Configuration Switch
1Mb
D8(OLW)
FF600000 - FF7FFFFF
Reserved
2Mb
FF800000 - FF8FFFFF
IP I/O/ID space
(up to 8 IP's)
1Mb
D16:D32
FF900000 - FF9FFFFF
RTC
1Mb
D8(OLW)
FFA00000 - FFAFFFFF
Parallel Port
1Mb
D8(OLW)
FFB00000 - FFBFFFFF
SCC
1Mb
D8(OLW)
FFC00000 - FFDFFFFF
Reserved
2Mb
FFE00000 - FFEFFFFF
VMEbus A16
1Mb (64K wraps)
D32
FFF00000 - FFFFFFFF
VMEbus A16
1Mb (64K wraps)
D16
7.2 Memory
Module
Base Address :
00000000
Size
:
Memory Module Dependent.
The BVME4000/6000 provides a site for BVM Memory Modules - refer to "Appendix C Memory
Module Pinout (on page 66)" for details. These modules are available in various configurations
(DRAM, SRAM, FLASH) and sizes and access speeds. Refer to the relevant Memory Module
documentation detailed in the "Appendix A Data Sheet & Manual References (on page 60)" section of
this manual for details of the configuration.
The Memory Module Interface is 32-bits wide (though byte addressed) and supports Cache LINE
transfers. Thus 'zero wait state' operation is supported; giving the MC68040/68060 optimum
performance of 2/1/1/1 clock cycles per transfer. Thus 16 bytes of data can be transferred in 5 clock
cycles (80Mbyte/sec @ 25MHz bus clock). Refer to the relevant Memory Module Manual for actual
memory performance.
The Memory Module provides a 'memory present' (/MEMOK) signal during the first cycle of an access
that it decodes. Thus the BVME4000/6000 address decoder automatically handles different size
Memory Modules. Any accesses (for addresses up to CFFFFFFF) that are not decoded by the
Memory Module, generate a VMEbus A32:D32 master access (except if VMELO is clear, in which
case the bottom 256Mb are decoded as on-board accesses only) - refer to "7.3.6 A32:D32 (on page
28)" for more details.
