ProDAQ 3150 User Manual
3150UM-01
Page 28
Bustec Production Ltd.
FC_AVAIL_RESET (0x20, read/write)
Reset function cards, the List Processor, the memories and the optional DSP
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Initial
0
0
0
0
0
0
0
0
read
function
F
C
8
A
V
A
IL
F
C
7
A
V
A
IL
F
C
6
A
V
A
IL
F
C
5
A
V
A
IL
F
C
4
A
V
A
IL
F
C
3
A
V
A
IL
F
C
2
A
V
A
IL
F
C
1
A
V
A
IL
E
N
A
B
L
E
/R
E
S
E
T
F
C
8
E
N
A
B
L
E
/R
E
S
E
T
F
C
7
E
N
A
B
L
E
/R
E
S
E
T
F
C
6
E
N
A
B
L
E
/R
E
S
E
T
F
C
5
E
N
A
B
L
E
/R
E
S
E
T
F
C
4
E
N
A
B
L
E
/R
E
S
E
T
F
C
3
E
N
A
B
L
E
/R
E
S
E
T
F
C
2
E
N
A
B
L
E
/R
E
S
E
T
F
C
1
write
function
re
s
re
s
re
s
re
s
re
s
re
s
re
s
re
s
E
N
A
B
L
E
/R
E
S
E
T
F
C
8
E
N
A
B
L
E
/R
E
S
E
T
F
C
7
E
N
A
B
L
E
/R
E
S
E
T
F
C
6
E
N
A
B
L
E
/R
E
S
E
T
F
C
5
E
N
A
B
L
E
/R
E
S
E
T
F
C
4
E
N
A
B
L
E
/R
E
S
E
T
F
C
3
E
N
A
B
L
E
/R
E
S
E
T
F
C
2
E
N
A
B
L
E
/R
E
S
E
T
F
C
1
FC1 ... FC8 AVAIL
signals availability of the corresponding front end card
read:
ENABLE FC1 ... FC8
reflects the ENABLE/RESET status of the corresponding front end card
write:
ENABLE FC1 ... FC8
drive directly the reset lines to the function card located at the specific
position. To enable the function cards a 1 has to be written.
MB_LP (0x22, read/write)
The MAIILBOX register set (MB_LP) consists of two 16-bit registers:
MB_LP_TO_VXI (read) and
MB_VXI_TO_LP (write)
A write to this mailbox register sets a bit in the MB_STATUS register and causes (if enabled) an interrupt to
the destination, which is cleared after the destination processor has read the message register.
MB_DSP (0x24, read/write)
A write to this mailbox register sets a bit in the MB_STATUS register and causes (if enabled) an interrupt to
the destination, which is cleared after the destination processor has read the message register.
The MAIILBOX register set (MB_LIST) consists of two 16-bit registers:
MB_DSP_TO_VXI (read) and
MB_VXI_TO_DSP (write)
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