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ProDAQ 3150 User Manual

3150UM-01

Page 40

Bustec Production Ltd.

Programming Information

Address Map

Internal

Address Start

Internal

Address End

Data

Width

Description

0x0040 0000

0x0043 FFFF

48 bit

SRAM (256K x 48)

0x0080 0000

0x0087 FFFF

8 bit

512K x 8 Flash Memory
(SHARC: Data [23:16])

0x00C0 0000

0x00FF FFFF

16 bit

Communication registers
(SHARC: Data[31:16] are used)

0x0100 0000

0x013F FFFF

16 bit

Local interface space
(SHARC: Data[31:16] are used)

0x0140 0000

0xFFFF FFFF

32 bit

Internal Bus
(SHARC: Data[47:16])

All addresses not explicitly specified are reserved for future use.

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Summary of Contents for ProDAQ 3150

Page 1: ...l service in house repair center WE BUY USED EQUIPMENT Sell your excess underutilized and idle used equipment We also offer credit for buy backs and trade ins www artisantg com WeBuyEquipment REMOTE INSPECTION Remotely inspect equipment before purchasing with our interactive website at www instraview com LOOKING FOR MORE INFORMATION Visit us on the web at www artisantg com for more information on ...

Page 2: ...quotations from a competitive source or used for manufacture by anyone other than Bustec Production Ltd The information herein has been developed at private expense and may only be used for operation and maintenance reference purposes or for purposes of engineering evaluation and incorporation into technical specifications and other documents which specify procurement of products from Bustec Produ...

Page 3: ...ions are made by persons other than authorized Bustec Production Ltd service personnel or without the written consent of Bustec Production Ltd Bustec Production Ltd expressly disclaims any liability to its customers dealers and representatives and to users of its product Also to any other person or persons for special or consequential damages of any kind and from any cause whatsoever arising out o...

Page 4: ...3 2 VXIbus Interface 16 3 2 1 VXIbus Configuration Registers 16 3 2 2 Interrupter 16 3 3 Memory 17 3 4 On board processor 17 3 5 Communication Arbitration Controller 17 3 6 The Trigger and Interrupt System 18 4 Programming Information 20 4 1 VXIbus Interface and Registers 20 4 1 1 VXIbus Configuration Registers 21 4 1 2 VXIbus Configuration Register Details 22 4 2 VXIbus Address Map 35 4 2 1 Funct...

Page 5: ... Module Cover 8 Figure 3 The module assembly 10 Figure 4 Location of Plug in Modules and Memory 11 Figure 5 Logical Address Selection 13 Figure 6 Simplified Block Diagram 15 Figure 7 DSP Plug in Module Block Diagram 39 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com ...

Page 6: ...Data Acquisition System which consists of the following components A ProDAQ Motherboard that installs into a VXI slot in a VXIbus chassis A ProDAQ Motherboard can be populated with a ProDAQ 3250 DSP Plug in Module ProDAQ 3150 Motherboard only a ProDAQ 3201 Voltage Reference Plug in Module optional and up to eight ProDAQ Function Cards The ProDAQ 3220 DSP Plug in Module that installs into the DSP P...

Page 7: ...hich should be left in place unless a ProDAQ function card is installed in the slot The ProDAQ function card slots are arranged in four stacks of two function cards each Unpacking and Inspection Before unpacking the ProDAQ module check the exterior of the shipping carton for any signs of damage All irregularities should be noted on the shipping bill The ProDAQ module is shipped in an antistatic pa...

Page 8: ...s apparent Reshipment Instructions Use the original packing material when returning a ProDAQ module to Bustec Production Ltd or calibration or servicing The original shipping carton and the instrument s plastic foam will provide the necessary support for safe reshipment If the original anti static packing material is unavailable wrap the ProDAQ module in anti static plastic sheeting and use plasti...

Page 9: ...2 Cover Screws 3 Cover Hooks Figure 2 Removing the ProDAQ Module Cover To remove the top cover remove the undercut flathead and two panhead screws that hold the cover in place and remove the cover by sliding it out of its position towards the VXIbus connectors and up Take special care about the hooks holding it into place Try not to lift the cover straight up See figure 2 for the location of the s...

Page 10: ...id bending the installed function cards Choose the stack and position lower or upper where you want to mount the function card If the stack in which the function card should be installed is covered by a double filler panel you have to remove it before installing the function card Remove the three 2 5mm panhead screws and the crinkle washers from the stack s standoffs Fig 3 Pos 9 and 10 for example...

Page 11: ... Panhead Screws 2 2 5mm Panhead Screws 3 Module Handle 4 Ring 5 Mounting Angle 6 2 5mm Panhead Screws 7 Standoff 8 Spacer 9 Crinkle Washer 10 2 5mm Panhead Screw 11 2mm Spacer Figure 3 The module assembly Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com ...

Page 12: ...ith only one function card each of the standoffs needs to be mounted with both spacers to cover the distance between the cards as well as the PCB thickness of the missing card If a stack is populated with two function cards only the bigger spacer must be mounted Fix any remaining function card again by mounting the three panhead screws on the standoffs re mount the front panel and the modules cove...

Page 13: ... connectors that need to be aligned and inserted into the motherboard sockets The VXIplug play drivers supplied with the module will automatically detect and configure an installed Voltage Reference Plug in Module Installing the ProDAQ DSP Plug in Module To install the ProDAQ DSP Plug in Module the top top cover of the module has to be removed as described earlier in this chapter Locate the positi...

Page 14: ...is reserved for the resource manager and address 255 is used to tell the resource manager to configure the board s logical address dynamically In this case a free logical address is assigned to the board by the resource manager The logical address of the board can be set by changing the setting of the 8 bit DIP switch on the back of the board See Figure 5 The Open or Off position of a switch corre...

Page 15: ...ProDAQ 3150 User Manual 3150UM 01 Page 14 Bustec Production Ltd Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com ...

Page 16: ...ule but provides in addition an enhanced VXIbus interface an on board processor and the option for a DSP Plug in module It is function card compatible to the ProDAQ 3120 Standard Motherboard Figure 6 Simplified Block Diagram FC 3 4 FC 5 6 FC 7 8 DSP opt On board Processor Communication Signaling Arbitration Voltage Reference opt V X I b u s P r o D A Q B u s FC 1 2 iBus Memory 2 Banks VXIbus Inter...

Page 17: ...located in the VXI configuration register set can define a set of function cards involved in a multicast write or a read from multiple function cards Broadcast write operations are also supported to initiate a common function in all function cards The ProDAQ 3150 Motherboard can be accessed from the VXIbus via byte word double word 32 bit and quad word 64 bit access in the A32 address space It occ...

Page 18: ...mmunication Arbitration Controller The communication arbitration controller provides mailbox registers for the communication between the different masters on the motherboard and implements a resource sharing protocol Each of the masters on the motherboard A VXIbus master via the VXIbus interface the on board processor and the optional DSP has two mailbox registers to communicate with the two other...

Page 19: ...ive trigger signals from other VXIbus devices or the controller VXIbus Interface The VXIbus interface features one trigger input line which can be used to generate an VXIbus interrupt The clock signals for the function cards are also routed via the switch matrix to allow them to be shut off in case no function card is fitted to a slot The switch matrix can be programmed to connect two or more of t...

Page 20: ...9 VXIbus TTL Trigger Line 5 In 16 MB Base Clock 40 MHz In 40 VXIbus TTL Trigger Line 6 In 17 FC 8 Clock Out 41 VXIbus TTL Trigger Line 7 In 18 FC 7 Clock Out 42 SYSCLK 16 MHz In 19 MB Base Clock 2 In 43 VXIbus ECL Trigger Line 0 In 20 VXIbus TTL Trigger Line 0 Out 44 CLK10 10 MHz In 21 FC 6 Clock Out 45 VXIbus ECL Trigger Line 1 In 22 FC 5 Clock Out 46 CLK 2 20 MHz In 23 VXIbus TTL Trigger Line 1 ...

Page 21: ...ProDAQ 3150 User Manual 3150UM 01 Page 20 Bustec Production Ltd Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com ...

Page 22: ...d short IO A16 for VXIconfig AM 0x0e or 0x0d or 0x0a or 0x09 normal A32 access AM 0x0b or 0x0f for A32 block transfers AM 0x08 or 0x0c for A32 D64 MBLT transfers Access to the module is with byte word double word and quad word transfers Unaligned data transfer i e access to byte 1 2 or 1 2 3 or 0 1 2 is not supported The module will respond with a bus error to such a transfer request A data transf...

Page 23: ...e FFFE 0x20 FC_AVAIL_RESET RW reset control of function cards and status of AVAIL bits 0x22 MB_LIST RW Mailbox VXItoLIST and LISTtoVXI 16 bit 0x24 MB_DSP RW Mailbox VXItoDSP and DSPtoVXI 16 bit 0x26 MB_STATUS R Mailbox STATUS register 0x28 JTAG RW JTAG interface for switch matrix loading 0x2a FCMOD RW FC CLK disable 0x2c FCMASK RW pattern mask for selecting concurrent write 0x2e VXI_TRIG_OUT RW VX...

Page 24: ...the logical address switch are off correspond to static address 255 the device acts as a dynamically configurable VXIbus device and a write to this register changes the logical address If any other address then 255 is choosen by setting the logical address switch the device acts as a static configured VXIbus device and a write to this register has no effect After a write operation the new logical ...

Page 25: ...ssed FPGAs are ready Ready after the state machines are initialized RLOG_SET read as 1 if the logical address is set VOFF_SET read as 1 if the A32 offset address is set PDB6 DRAM Bank 1 memory ID bit 6 Bank1 upper 72 pin SO DIMM PDB7 DRAM Bank 1 memory ID bit 7 Bank1 upper 72 pin SO DIMM PDB6 DRAM Bank 2 memory ID bit 6 Bank2 lower 72 pin SO DIMM PDB7 DRAM Bank 2 memory ID bit 7 Bank2 lower 72 pin...

Page 26: ...led Any attempt to enable the A32 addressing mode without prior offset register configuration will fail Offset 0x6 read write Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Operation RW RW RW RW RW RW RO RO RO RO RO RO RO RO RO RO Initial 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Compare A31 A30 A29 A28 A27 A26 Name Offset 0 Defines the offset of the boards address space in the VXIbus address space Depending on ...

Page 27: ...0 0 0 1 0 0 0 1 Name Firmware Main Version Firmware Revision Hardware Main Version Hardware Revision InterStatus 0x1A read Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Operation RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Initial 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SW MBX DSP MBX LP TM Name Cause Status LogAddress TM Interrupt is caused by a request from the trigger switch matrix MBX LP Interupt Requ...

Page 28: ...upter enable 1 disables 0 enabled Interrupt Mask enable mask enabled if bit is set to 0 TM enables interrupt requests from the trigger switch matrix MBX LP enables interrupt requests from the LP VXI mailbox register MBX DSP enables interrupt requests from the DSP VXI mailbox register SW causes an interrupt by writing a 0 for testing only Note a Hard reset power up SYSRESET and a soft reset reset v...

Page 29: ...NABLE RESET status of the corresponding front end card write ENABLE FC1 FC8 drive directly the reset lines to the function card located at the specific position To enable the function cards a 1 has to be written MB_LP 0x22 read write The MAIILBOX register set MB_LP consists of two 16 bit registers MB_LP_TO_VXI read and MB_VXI_TO_LP write A write to this mailbox register sets a bit in the MB_STATUS...

Page 30: ... RW RW RW RW RW RW Initial 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Name RCena TSMena VXITOena SW1 SW0 JTLOC TDO TDI TMS TCLK TRST TRST reset of the Trigger Switch Matrix JTAG interface For a proper reset write a 1 and after 100µs a 0 into that register bit TCLK JTAG clock Note a clock pulse is generated automatically 75 ns if a 1 is written into that register TMS to change the state machine output is inve...

Page 31: ...15 8 used to indicate selected channels for read Bit 7 0 selected channels for write operation VXI_TRIG_OUT 0x2E read write Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Operation R R R R R RW RW RW RW RW RW RW RW RW RW RW Initial 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Name TMO 2 TMO 1 TMO 0 FCTI 7 FCTI 6 FCTI 5 FCTI 4 FCTI 3 FCTI 2 FCTI 1 FCTI 0 Read FCTI 0 7 Status of the Function card trigger input actual...

Page 32: ...ot M0 res res res res res LIST RESET LIST Boot M1 LIST Boot M0 Read Function 0 0 0 DSP AVAIL SW701_2 DSP RESET 2 DSP Boot M1 DSP Boot M0 0 0 0 LIST AVAIL SW701_1 LIST RESET 1 LIST Boot M1 LIST Boot M0 1 With switch SW701_1 open high RESET condition after power up with switch closed RUN condition after power up 2 With switch SW701_2 open high RESET condition after power up with switch closed RUN co...

Page 33: ...P EEPROM SYSFAIL OUT Test flag to generate a VME SYSFAIL signal if enabled VME_ORDER controls the 16 bit word order during a D32 BLT32 access to or from the FC card if 0 the lower 16 bit will be transfered first like the old LMB example write with D32 0x11112222 to one FC card first 16 bit word to the FC card 0x2222 second 16 bit word to the FC card 0x1111 if 1 the upper 16 bit will be transfered ...

Page 34: ...R bit write 1 function res res res res res res res res res res res res VXI FC_D Stack REQUEST bit VXI FC_C Stack REQUEST bit VXI FC_B Stack REQUEST bit VXI FC_A Stack REQUEST bit Power up or VXI reset condition 0x0000 Stack FC_D FC 8 and FC 7 Stack FC_C FC 6 and FC 5 Stack FC_B FC 4 and FC 3 Stack FC_A FC 2 and FC 1 FC_STACK_LOCK_CLR 0x3A write Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 write 1 fun...

Page 35: ...STRER bit VXI FC_RESET MASTER bit VXI VREF MASTER bit write function res res res res res res res res res res res res VXI JTAG REQUEST bit VXI RAPID REQUEST bit VXI FC_RESET REQUEST bit VXI VREF REQUEST bit Power up or VXI reset condition 0x0000 SOURCE_ARB_CLR 0x3E write Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 write function res res res res res res res res res res res res VXI JTAG clear MASTER bi...

Page 36: ... Trigger Interface 0x00300000 Trigger status register 32 bit word with update 0x00300004 Trigger rapid connect interface 32 bit word 0x00300008 Trigger status register without update e g IRQ response 0x00320000 0x0032FFFF Voltage Reference Interface 0x00320000 Voltage Reference R W MB buffer 0x00320004 Voltage Reference ID read only 0x00320008 Voltage Reference Module Access 0x00330000 0x003BFFFF ...

Page 37: ...k Transfer Read n x two 16 bit words D32 BLT write FC Block Transfer Write n x two 16 bit words Note The 32 bit to two 16 bit word transfer order depends on the VME_ORDER bit in the Util register Multiple Function Card Access By selecting functions cards in the FCMASK register multiple function cards can be accessed simultaneously In this mode VXIbus D32 data cycles are mapped as D32 Single read 2...

Page 38: ...rigger status register with update 32 bit word Holds the actual level of the Trigger lines Trigger status register without update 32 bit word read only An interrupt request from the trigger matrix updates the register to allow the application program to determine the interrupting source The register has the following bit assignment Bit 31 30 29 28 27 26 25 24 Name 1 1 TMO 2 TMO 1 TMO 0 1 ECLtrig 1...

Page 39: ... TTLtrig 0 7 Status of the VXIbus TTL trigger lines FCtrgOut 0 7 Status of the function card output trigger lines FCtrgIn 0 7 Status of the function card input trigger lines Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com ...

Page 40: ...one for the internal bus on the motherboard iBus amd one for the VXIbus local bus The interface for the iBus also implements a set of communication registers Figure 7 DSP Plug in Module Block Diagram The communication registers provide mailbox registers for the communication with the on board processor or a host and also registers for motherboard status and motherboard resources IBus Interface SHA...

Page 41: ...7 FFFF 8 bit 512K x 8 Flash Memory SHARC Data 23 16 0x00C0 0000 0x00FF FFFF 16 bit Communication registers SHARC Data 31 16 are used 0x0100 0000 0x013F FFFF 16 bit Local interface space SHARC Data 31 16 are used 0x0140 0000 0xFFFF FFFF 32 bit Internal Bus SHARC Data 47 16 All addresses not explicitly specified are reserved for future use Artisan Technology Group Quality Instrumentation Guaranteed ...

Page 42: ...F_IDENT R VREF identifier 0x00C0 0014 VREF_ACCESS RW VREF access 0x00C0 0016 reserved reserved 0x00C0 0018 TRIG_IN_EN_IRQ Trigger LIST DSP IRQ2 Enable register 0x00C0 001A TRIG_OUT Trigger SET and status register TM2 0 FC_TRIG_IN0 7 0x00C0 001B reserved reserved 0x00C0 001C reserved reserved 0x00C0 001D reserved reserved 0x00C0 001E reserved reserved 0x00C0 001F reserved reserved 0x00C0 0020 MODE ...

Page 43: ...MB_VXI 0x00C0 0002 read write The MAIILBOX register consists of two 16 bit registers MB_VXI_TO_DSP read and MB_DSP_TO_VXI write A write to this mailbox register sets a bit in the MB_STATUS register and causes if enabled an interrupt to the destination which is cleared after the destination processor has read the message register MB_DSP 0x00C0 0004 read write The MAIILBOX register set consists of t...

Page 44: ...C 1 write function res res res res res res res res ENABLE NOT RESET FC 8 ENABLE NOT RESET FC 7 ENABLE NOT RESET FC 6 ENABLE NOT RESET FC 5 ENABLE NOT RESET FC 4 ENABLE NOT RESET FC 3 ENABLE NOT RESET FC 2 ENABLE NOT RESET FC 1 FC1 FC8 AVAIL signals availability of the corresponding front end card read ENABLE FC1 FC8 reflects the ENABLE RESET status of the corresponding front end card write ENABLE ...

Page 45: ...R bit VXI FC_RESET MASTER bit VXI VREF MASTER bit write function res res res res res res res res LIST JTAG REQUEST bit LIST RAPID REQUEST bit LIST FC_RESET REQUEST bit LIST VREF REQUEST bit res res res res Power up or VXI reset condition 0x0000 SOURCE_ARB_CLR 0x00C0 000A write Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 write function res res res res res res res res LIST JTAG clear MASTER bit LIST R...

Page 46: ...nd have caused an interrupt are active The bits which have caused an interrupt have to be cleared by disabling the appropriated bit TRIG_OUT 0x00C0 001A read write Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Operation RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW Initial 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Name LIST_FLAG2 _IRQ2 FL2 FL1 FL0 TMO 2 TMO 1 TMO 0 FCTI 7 FCTI 6 FCTI 5 FCTI 4 FCTI 3 FCTI 2 FC...

Page 47: ...7 6 5 4 3 2 1 0 Operation RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RW Initial 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Name reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved DSP_RESET DSP_RESET ored with the VXI DSP Reset FC_MASK_BROAD 0x00C0 0021 read write Used for broadcast write operations in Mode 7 only LIST Bit 1...

Page 48: ...R bit write 1 function res res res res DSP FC_D Stack REQUEST bit DSP FC_C Stack REQUEST bit DSP FC_B Stack REQUEST bit DSP FC_A Stack REQUEST bit res res res res res res res res Power up or VXI reset condition 0x0000 Stack FC_D FC 8 and FC 7 Stack FC_C FC 6 and FC 5 Stack FC_B FC 4 and FC 3 Stack FC_A FC 2 and FC 1 FC_STACK_LOCK_CLR 0x00C00023 write Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 write...

Page 49: ...t PDB7 DRAM Bank 2 memory ID bit 7 Bank2 lower 72 pin SO DIMM PDB6 DRAM Bank 2 memory ID bit 6 Bank2 lower 72 pin SO DIMM PDB7 DRAM Bank 1 memory ID bit 7 Bank1 lower 72 pin SO DIMM PDB6 DRAM Bank 1 memory ID bit 6 Bank1 lower 72 pin SO DIMM FC_D_ERR reflects the hardware signal FC_ERR of STACK FCD FC7 FC8 FC_C_ERR reflects the hardware signal FC_ERR of STACK FCC FC5 FC6 FC_B_ERR reflects the hard...

Page 50: ...A26 A25 A24 0 0 1 0 0 0 FC RD x FC card AS cycle only write 0 0 1 0 0 1 FC RD x FC card AS cycle and hold AS only write 0 0 1 0 1 0 x x FC card AS disconnect cycle clr AS 0 0 1 0 1 1 x x Reserve 0 0 1 1 0 0 x x FC card normal Read Write DS cycle 0 0 1 1 0 1 x x FC card pipe Read DS cycle read FC Latch and then start DS cycle 0 0 1 1 1 0 x x FC card Read Latch cycle read FC Latch A23 A16 used as FC...

Page 51: ..._ PAGE SET_ PAGE 1 DRAM Bank 2 A PAGE bit will be set during a DRAM read cycle if addr Bit 25 is 1 If this bit is SET then the DRAM bank gets locked and access to the DRAM is faster and locked You can CLEAR this PAGE bit during a DRAM read cycle if addr Bit 26 is 1 Example define DRAM_ADDR00_ENPAGE 0x62000000 define DRAM_ADDR00_DISPAGE 0x64000000 FC_MODE7_LOOP R2 DM DRAM_ADDR00_ENPAGE DM FC_AS_WRI...

Page 52: ...ase address 0x0100 0000 Address Mnemonic DSP RW Function 0x0100 0000 LOC_CONTROL RW LOCAL Bus interface Control register 0x0100 0002 LOC_P2A_OUT RW Output register to set VXI Local bus P2A lines 0x0100 0003 LOC_P2C_OUT RW Output register to set VXI Local bus P2C lines 0x0100 0004 LOC_P2A_IN R Status of VXI Local bus P2A lines 0x0100 0005 LOC_P2C_IN R Status of VXI Local bus P2C lines Note For acce...

Page 53: ...SC0 11 ENABLE_P2A_ OUT_REG enables LOC_P2A_OUT register outputs to lines VXI LBUSA0 11 TRANSMIT_ LINK3 1 SHARC Link3 transmit data 0 SHARC Link3 receive data ENABLE _LINK3 enables SHARC Link3 in outputs to lines VXI LBUSC6 11 TRANSMIT_ LINK2 1 SHARC Link2 transmit data 0 SHARC Link2 receive data ENABLE _LINK2 enables SHARC Link2 in outputs to lines VXI LBUSC0 5 TRANSMIT_ LINK1 1 SHARC Link1 transm...

Page 54: ... L1DATA0 VXI LBUSA8 17A L1DATA1 VXI LBUSA9 18A L1DATA2 VXI LBUSA10 20A L1DATA3 VXI LBUSA11 21A Sharc Link 2 VXI Local bus P2 connector L2ACK VXI LBUSC0 5C L2CLK VXI LBUSC1 6C L2DATA0 VXI LBUSC2 8C L2DATA1 VXI LBUSC3 9C L2DATA2 VXI LBUSC4 11C L2DATA3 VXI LBUSC5 12C Sharc Link 3 VXI Local bus P2 connector L3ACK VXI LBUSC6 14C L3CLK VXI LBUSC7 15C L3DATA0 VXI LBUSC8 17C L3DATA1 VXI LBUSC9 18C L3DATA2...

Page 55: ...OUT 7 P2C_ OUT 6 P2C_ OUT 5 P2C_ OUT 4 P2C_ OUT 3 P2C_ OUT 2 P2C_ OUT 1 P2C_ OUT 0 P2C_OUT 0 11 1 sets the VXI Local bus signals LBUSC0 11 if P2C FET driver is enabled and ENABLE_P2C_ OUT_REG is enabled ENABLE_LOC_P2C 1 and ENABLE_P2C_ OUT_REG 1 LOC_P2A_IN 0x0100 0004 read Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Operation R R R R R R R R R R R R R R R R Name 0 0 0 0 P2A_ IN11 P2A_ IN10 P2A_ IN9 ...

Page 56: ...l service in house repair center WE BUY USED EQUIPMENT Sell your excess underutilized and idle used equipment We also offer credit for buy backs and trade ins www artisantg com WeBuyEquipment REMOTE INSPECTION Remotely inspect equipment before purchasing with our interactive website at www instraview com LOOKING FOR MORE INFORMATION Visit us on the web at www artisantg com for more information on ...

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