Bitwise QuickUSB, User Manual

Page: 23 / 74

Designing Hardware for QuickUSB
Asynchronous Slave FIFO I/O Model
This I/O Model performs all transfers asynchronously using only the
rising/falling edge of the nSLRD or nSLWR line to perform the transfer. This
model is configured by setting the
SETTING_FIFO_CONFIG bits IFCFG (bits 0-1)
to ‘11’ to go to Slave FIFO Mode and ASYNC (bit 3) to ‘1’ to make all
transactions asynchronous.
t
WRpwl
nSLRD RDY0
nSLWR RDY1
FLAGC (nEMPTY) CTL2
FLAGB (nFULL) CTL1
DATA PB
Name PIN
Z
Write Cycle
Data0
t
SFD
t
WRpwh
t
FDH
Z Data1 Z Data2
t
XFDWR
FIFOADR[1:0] PA5:PA4
10
X
t
SFA
t
FAH
nSLOE PA2
t
FAH
nPKTEND PA6
t
PEpwl
t
PEpwh
Z
X
t
XFLG
Signifies QuickUSB Read from the Data Bus
nSLCS PA7
t
RDpwl
Z
Read Cycle
Data0
t
XFDRD
t
RDpwh
Data1 Data2
t
XFLG
nSLRD RDY0
nSLWR RDY1
FLAGC (nEMPTY) CTL2
FLAGB (nFULL) CTL1
DATA PB
Name PIN
Z
nSLOE PA2
FIFOADR[1:0] PA5:PA4 00 X
X
t
SFA
t
FAH
t
FAH
t
OEon
t
OEoff
t
XFD
t
XFLG
X
X
X
nPKTEND PA6
Signifies QuickUSB Write to the Data Bus
nSLCS PA7
Figure 2 - Asynchronous Slave FIFO I/O Model Timing Diagrams
Parameter Description Min Max Unit
tRDpwl SLRD Pulse Width Low 50 ns
tRDpwh SLRD Pulse Width High 50 ns
tWRpwl SLWR Pulse Width Low 50 ns
tWRpwh SLWR Pulse Width High 70 ns
tSFD SLWR to FIFO DATA Set-up Time 10 ns
tFDH FIFO DATA to SLWR Hold Time 10 ns
tXFLG SLRD to Flags Output Propagation Delay 70 ns
tXFDWR SLWR to Flags Output Propagation Delay 70 ns
tXFDRD SLRD to FIFO Data Output Propagation Delay 15 ns
tOEon SLOE On to FIFO Data Valid 10.5 ns
tOEoff SLOE Off to FIFO Data Hold 10.5 ns
tSFA FIFOADR/nSLCS to SLRD/SLWR/PKTEND
Set-up Time
10 ns
tFAH SLRD/SLWR/PKTEND to FIFOADR/nSLCS
Hold Time
10 ns
tPEpwl PKTEND Pulse Width Low 50 ns
tPEpwh PKTEND Pulse Width High 50 ns
tXFL PKTEND to Flags Output Propagation Delay 115 ns
Table 5 – Asynchronous Slave FIFO Timing Parameters
High Speed Parallel Port 19