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Designing Hardware for QuickUSB

Full Handshake I/O Model

The full handshake I/O model is ideal for connecting a device that has a very
slow or variable transfer time. The module checks the state of the READY signal
before each state transition and thereby guarantees that the module and target
will be properly synchronized at all times.
This I/O model is implemented in the QuickUSB firmware file

‘quickusb-fullhs vX.XX.qusb’ where X.XX is the firmware version number.

Command Transfers

IFCLK

IFCLK

X

Data[N]

Z

t

DAH

t

SGD

CMD_DATA

CTL0

REN

CTL1

WEN

CTL2

nREN

CTL3

nWEN

CTL4

RDYTST

CTL5

GPIFADR

GPIFADR

FD

PB, PD

Name

Pin

Z

Z

X

Data[N]

t

XGD

Z

Addr[N]

Read Cycle

Write Cycle

READY

RDY0

t

XCTL

t

SRY

t

XCTL

Addr[N+1]

X

Addr[N]

t

XCTL

t

RYH

Addr[N+1]

X

t

SGA

t

SRY

t

RYH

t

XCTL

t

SRY

t

RYH

t

SRY

t

RYH

t

SGA

Signifies QuickUSB Read
from the Data Bus

Signifies QuickUSB Write
to the Data Bus

t

XCTL

t

XCTL

Data Transfers

IFCLK

IFCLK

Addr0

X

t

DAH

t

SGD

CMD_DATA

CTL0

REN

CTL1

WEN

CTL2

nREN

CTL3

nWEN

CTL4

RDYTST

CTL5

GPIFADR

GPIFADR

FD

PB, PD

Name

Pin

Z

Data0

Read Cycle

X

Z

t

SGA

READY

RDY0

Addr1

Data1

Addr[N]

Data[N]

Z

Z

t

SRY

t

RYH

…

Addr[N+1]

…

t

XCTL

t

XCTL

t

XCTL

t

IFCLK

t

SRY

t

RYH

Signifies QuickUSB Read from the Data Bus

Full Speed, Byte Wide: N = 63

High Speed, Byte Wide: N = 511

Full Speed, Word Wide: N = 31

High Speed, Word Wide: N=255

IFCLK

IFCLK

Addr0

X

t

XGD

CMD_DATA

CTL0

REN

CTL1

WEN

CTL2

nREN

CTL3

nWEN

CTL4

RDYTST

CTL5

GPIFADR

GPIFADR

FD

PB, PD

Name

Pin

Z

Data0

Write Cycle

X

Z

t

SGA

READY

RDY0

Addr1

Addr[N]

Z

Z

t

SRY

t

RYH

Addr[N+1]

t

XCTL

t

XCTL

t

IFCLK

Data[N]

t

SRY

t

RYH

Data1

t

XGD

t

XCTL

…

Signifies QuickUSB Write to the Data Bus

Full Speed, Byte Wide: N = 63

High Speed, Byte Wide: N = 511

Full Speed, Word Wide: N = 31

High Speed, Word Wide: N=255

High Speed Parallel Port

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Summary of Contents for QuickUSB

Page 1: ...Guide 6489 Calle Real Suite E Goleta CA 93117 Voice 805 683 6469 Fax 805 683 4833 Toll Free 800 224 1633 Web Site www bitwisesys com Information info bitwisesys com Technical Support support bitwisesy...

Page 2: ...tems and is protected by United States and international copyright laws Use disclosure or reproduction is prohibited without the prior express written permission of Bitwise Systems except as agreed in...

Page 3: ...l Purpose I O Pins 21 RS 232 21 I2C 21 SPI 22 QuickUSB Pin Definitions 23 Using the QuickUSB Library 39 Overview 39 How to Communicate with a Module 39 System Considerations 40 Blocking versus Non blo...

Page 4: ...60 QuickUsbAsyncWait 61 General Purpose I O 62 QuickUsbReadPortDir 62 QuickUsbWritePortDir 62 QuickUsbReadPort 63 QuickUsbWritePort 63 RS 232 64 QuickUsbSetRs232BaudRate 64 QuickUsbGetNumRS232 64 Quic...

Page 5: ...an browse www usb org and learn just about everything that there is to know about USB Just be careful because you can easily get distracted from what you really need to accomplish USB Nomenclature Con...

Page 6: ...mended Another way to mitigate transfer latency issues is to minimize the amount of time that the USB subsystem waits to schedule USB packets You can accomplish this using asynchronous function calls...

Page 7: ...n once the host configures the module This behavior is required by the USB specification The QuickUSB module incorporates a current limiting circuit that will shut down the VBUS pins on an over curren...

Page 8: ...dels Overview The high speed parallel port HSPP is an 8 or 16 bit port that is used to transfer high speed data between the host PC and your device The WORDWIDE setting controls the data element width...

Page 9: ...D and the address bus GPIFADR to read and write data to and from the target hardware The QuickUsbReadCommand and QuickUsbWriteCommand functions are used to perform command transfers They transfer data...

Page 10: ...FCLK All CMD_DATA All REN or nREN All WEN or nWEN All nEMPTY FIFO Block nFULL FIFO Block nOE FIFO Block Table 1 GPIF Master Mode I O Connections GPIF Master Mode Timing Parameters Internally Sourced I...

Page 11: ...RANSFER LENGTHS THAT MAY RESULT IN A FATAL SOFTWARE ERROR WHICH MAY CRASH YOUR COMPUTER The simplest valid transfer length calculation is to request data transfer lengths in multiples of 512 bytes for...

Page 12: ...GPIFADR GPIFADR FD PB PD Name Pin Z Data0 Write Cycle Addr1 Data1 Addr2 Addr3 Addr4 Addr N 1 Addr N X Data2 Data3 Data4 Data N 1 Data N Z tSGA nEMPTY RDY0 nFULL RDY1 X tXCTL tIFCLK Addr N 1 X X X tXC...

Page 13: ...s to the QuickUSB module Please note the FIFO timing requirements given in the Data Transfers section This I O model is implemented in the QuickUSB firmware file quickusb fifohs vX XX qusb where X XX...

Page 14: ...peed Byte Wide N 63 High Speed Byte Wide N 511 Full Speed Word Wide N 31 High Speed Word Wide N 255 Addr1 Addr2 Addr N 1 Z tSGA IFCLK IFCLK tXGD CMD_DATA CTL0 REN CTL1 WEN CTL2 nREN CTL3 nWEN CTL4 nOE...

Page 15: ...Y tRYH tSRYtRYH tSGA Signifies QuickUSB Read from the Data Bus Signifies QuickUSB Write to the Data Bus tXCTL tXCTL Data Transfers IFCLK IFCLK Addr0 X tDAH tSGD CMD_DATA CTL0 REN CTL1 WEN CTL2 nREN CT...

Page 16: ...GTHS THAT MAY RESULT IN A FATAL SOFTWARE ERROR WHICH MAY CRASH YOUR COMPUTER The simplest valid transfer length calculation is to request data transfer lengths in multiples of 512 bytes for Hi Speed m...

Page 17: ...yte Wide N 63 High Speed Byte Wide N 511 Full Speed Word Wide N 31 High Speed Word Wide N 255 IFCLK IFCLK Addr0 X tXGD CMD_DATA CTL0 REN CTL1 WEN CTL2 nREN CTL3 nWEN CTL4 nOE CTL5 GPIFADR GPIFADR FD P...

Page 18: ...VALID TRANSFER LENGTHS THAT MAY RESULT IN A FATAL SOFTWARE ERROR WHICH MAY CRASH YOUR COMPUTER The simplest valid transfer length calculation is to request data transfer lengths in multiples of 512 by...

Page 19: ...TL5 GPIFADR GPIFADR FD PB PD Name Pin Z Data0 Write Cycle Addr1 Data1 Addr2 Addr3 Addr4 Addr N 1 Addr N X Data2 Data3 Data4 Data N 1 Data N Z tSGA nEMPTY RDY0 nFULL RDY1 X tXCTL tIFCLK Addr N 1 X X X...

Page 20: ...g The following signals are required for slave mode operation Pin Name Alternate Name Description Default Config IFCLK IFCLK Clock for synchronous I O Rising edge FD 15 0 PD 7 0 PB 7 0 Bi directional...

Page 21: ...SRD tRDH FIFOADR 1 0 PA5 PA4 tSFA tFAH tFAFLG X X tFAFD tSRD tRDH tSFA tSRD tRDH X tFAH tFAFD tFAFLG X X X Z Data0 Data1 Data2 Data3 Data N 1 Data N 00 X Z X 00 nPKTEND PA6 Signifies QuickUSB Write to...

Page 22: ...s tXFD Clock to FIFO Data Output Propagation Delay 11 15 ns tSWR SLWR to Clock Set up Time 18 1 12 1 ns tWRH Clock to SLWR Hold Time 0 3 6 ns tSFD FIFO Data to Clock Set up Time 9 2 3 2 ns tFDH Clock...

Page 23: ...OADR 1 0 PA5 PA4 00 X X tSFA tFAH tFAH tOEon tOEoff tXFD tXFLG X X X nPKTEND PA6 Signifies QuickUSB Write to the Data Bus nSLCS PA7 Figure 2 Asynchronous Slave FIFO I O Model Timing Diagrams Parameter...

Page 24: ...FIFOADR 1 RDY1 PA5 TXE CTL2 RXF CTL1 FD 7 0 PB 7 0 Name PIN X X Signifies QuickUSB Write to the Data Bus tXFDRD X X tADRFLG X tWRpwl RD SLOE RDY0 PA2 WR FIFOADR 1 RDY1 PA5 TXE CTL2 RXF CTL1 FD 7 0 PB...

Page 25: ...LK nCONFIG nCONFIG PROGRAM nSTATUS nSTATUS INIT CONF_DONE CONF_DONE DONE Table 6 FPGA Configuration Signals General Purpose I O Pins The QuickUSB Module implements General Purpose I O Pins on Ports A...

Page 26: ...I PE0 MISO PE5 X X D N 7 X X Signifies QuickUSB Write to MOSI D N 6 D 0 2 D 0 1 D 0 0 D N 5 D N 4 D N 3 D N 2 D N 1 SCLK PE1 Name Pin Write Read Cycle nSS 9 0 PA 7 0 PE 7 6 MOSI PE0 MISO PE5 Dout N 7...

Page 27: ...tion is currently unused 83 5 PA1 nSS3 nINT1 I O Port A Bit 1 Multifunction Pin PA1 default is a bi directional general purpose I O pin nSS3 is the SPI slave select signal for Address 3 Automatically...

Page 28: ...1 0 PA5 default is a bi directional general purpose I O pin Enabled when SETTING_FIFO_CONFIG 1 0 00 or 10 nSS7 is the SPI slave select signal for Address 7 See Note for nSS2 FIFOADR1 is an input only...

Page 29: ..._CONFIG 1 0 00 FD0 default is the bi directional GPIF data bus low byte Enabled when SETTING_FIFO_CONFIG 1 0 10 45 23 PB1 FD1 I O Port B Bit 1 Multifunction Pin whose function is selected by SETTING_F...

Page 30: ...when SETTING_FIFO_CONFIG 1 0 00 FD6 default is the bi directional GPIF data bus low byte Enabled when SETTING_FIFO_CONFIG 1 0 10 57 35 PB7 FD7 I O Port B Bit 7 Multifunction Pin whose function is sel...

Page 31: ...abled when SETTING_FIFO_CONFIG 1 0 00 GPIFADR4 default is a GPIF address output pin Enabled when SETTING_FIFO_CONFIG 1 0 10 77 49 PC5 GPIFADR5 I O Port C Bit 5 Multifunction Pin whose function is sele...

Page 32: ...IDE 0 FD9 default is the bi directional GPIF data bus Enabled when SETTING_FIFO_CONFIG 1 0 10 and when SETTING_WORDWIDE 1 104 61 PD2 FD10 I O Port D Bit 2 Multifunction Pin whose function is selected...

Page 33: ...ING_WORDWIDE 0 FD13 is the bi directional GPIF data bus Enabled when SETTING_FIFO_CONFIG 1 0 10 and when SETTING_WORDWIDE 1 123 69 PD6 FD14 I O Port D Bit 6 Multifunction Pin whose function is selecte...

Page 34: ...clock output signal for the SPI port Automatically switches functionality when using the SPI commands 110 62 PE2 nCE I O Port E Bit 2 Multifunction Pin PE2 is a bi directional general purpose I O por...

Page 35: ...O if using SPI nSS0 nSS1 115 72 PE7 GPIFADR8 nSS1 I O Port E Bit 7 Multifunction Pin PE7 is a bi directional general purpose I O port Enabled when SETTING_FIFO_CONFIG 1 0 00 or 11 GPIFADR8 default is...

Page 36: ...sitive This function is currently unused N A 12 RXD_0 Input Serial Port 0 RxD Serial Port 0 RxD Note If U1 is populated with a Linear Tech part QuickUSB Module uses EIA TIA 564 Levels If U1 is populat...

Page 37: ...tput 2 Multifunction Pin whose function is selected by SETTING_FIFO_CONFIG 1 0 CTL2 default is a GPIF output signal whose function WEN is waveform specific Enabled when SETTING_FIFO_CONFIG 1 0 10 WEN...

Page 38: ...TST is the Ready Test output signal for the Full Handshake I O Model RDYTST outputs the correct handshake waveform for the READY line so it can be connected to READY to test the Full Handshake functio...

Page 39: ...ifunction Pin whose function is selected by SETTING_FIFO_CONFIG 1 0 RDY1 default is a GPIF input whose function nFULL is waveform specific Enabled when SETTING_FIFO_CONFIG 1 0 10 nFULL is an active lo...

Page 40: ...D6 I O 88 N A D7 I O 8051 Data Bus 8051 Data Bus Bi directional bus used for external 8051 program and data memory High Impedance when inactive Active only for external bus accesses Driven low in susp...

Page 41: ...A VCC Power VCC VCC Connect VCC to 3 3V Power Source 107 N A VCC Power VCC VCC Connect VCC to 3 3V Power Source 10 N A AVCC N A Analog VCC ANALOG VCC connect to 3 3V power source Provides power to th...

Page 42: ...116 N A GND N A Ground Ground 125 N A GND N A Ground Ground 14 N A NC N A No Connect This pin must be left open 15 N A NC N A No Connect This pin must be left open 16 N A NC N A No Connect This pin mu...

Page 43: ...uickUSB Library directly from your programming language For instance your application will include a file that has all the QuickUSB function declarations then from your code you would call the appropr...

Page 44: ...lows a user to make both Blocking QuickUsbReadData and QuickUsbWriteData and Non blocking QuickUsbReadDataAsync and QuickUsbWriteDataAsync data transfer calls When called the Blocking functions will i...

Page 45: ...ters For example after executing this function with one module connected nameList will contain QUSB 0 0 0 If there are two devices plugged in nameList will contain QUSB 0 0QUSB 1 0 0 Notes This routin...

Page 46: ...string descriptor index given in the following table buffer A PCHAR that points to a buffer in which to place the string descriptor The buffer should be at least 128 bytes long length A WORD that con...

Page 47: ...major version number minor A PWORD that points to a variable in which to place the minor version number build A PWORD that points to a variable in which to place the build number Returns A LONG that...

Page 48: ...aining 1 Notes Error Code Error Description 0 No error 1 Out of memory Please free some memory and try again 2 Cannot open module 3 Cannot find specified QuickUSB module Please check the specified mod...

Page 49: ...ion 0 Output 1 Input Bit 13 12 Type Defines EP2 Type 00 Invalid 01 Isochronous 10 Bulk 11 Interrupt Bit 11 Size Sets Size of EP2 Buffer 0 512 Bytes 1 1024 Bytes Bit 10 Unused R O 0 Bit 9 8 Buf EP2 Buf...

Page 50: ...Sets the FIFO configuration Controls the FX2 IFCONFIG register MSB FIFOINPOLAR Slave FIFO Interface Pins Polarity Bit Definitions Bit 15 14 Unused R O 0 Bit 13 PKTEND FIFO Packet End Polarity 0 Activ...

Page 51: ...0 Force full speed 12Mbps 1 Allow high speed 480Mbps Bit 14 8 Reserved for future use LSB CPUCS Bit definitions Bit 7 6 Unused R O 0 Bit 5 Reserved do not change Bit 4 3 CLKSPD CPU clock speed 00 12MH...

Page 52: ...l completion 00001010 Slave wait 00001011 Timeout LSB I2CTL I2C Compatible Bus Control Bit definitions Bit 7 2 Reserved for future use Bit 1 Reserved Do not change Bit 0 400KHz Sets I2C bus clock spee...

Page 53: ..._PORTE Configures Port E default state Reading a bit from IOE returns the logic level of the port pin that is two CLKOUT clocks old Writing a register bit to IOE writes to the port pin latch The port...

Page 54: ...FLAGA and FLAGB Pin Configuration Bit 15 12 FLAGB FLAGB Show the status of the FIFO Flag selected by programming these bits with the code given below Bit 11 8 FLAGA FLAGA shows the status of the FIFO...

Page 55: ...settings Parameters hDevice A HANDLE that was returned from a call to QuickUsbOpen address A WORD containing the setting address number setting A PWORD pointing to a variable in which to place the val...

Page 56: ...which to place the value of the default if successful Returns A LONG that is non zero on success zero 0 on failure Notes None QuickUsbWriteDefault Purpose To write QuickUSB module defaults The default...

Page 57: ...guration file and read a block into a buffer 3 Call QuickUsbWriteFpgaData and pass in the data from the file Repeat this process until the entire file is sent Of course the last block will probably be...

Page 58: ...es The maximum data length is 64 A call to QuickUsbStartFpgaConfiguration must precede FPGA configuration QuickUsbIsFpgaConfigured Purpose Check to see if the FPGA is configured Parameters hDevice A H...

Page 59: ...not be incremented after each read data A pointer to a buffer in which to place data read from the high speed parallel port See notes length A PWORD pointing to a WORD containing the number of bytes t...

Page 60: ...then the address will not be incremented after each write data A pointer to a buffer containing the data to write to the high speed parallel port See notes length A WORD containing the number of bytes...

Page 61: ...nections In order to obtain the maximum performance call this function with the largest appropriate length value Each call to this function will incur one call latency delay regardless of the transfer...

Page 62: ...ength is 16 megabytes 16777216 bytes The data buffer can contain data values of any type In master mode data values are transferred over the high speed parallel port with the CMD_DATA line set to 0 In...

Page 63: ...the operating system Failure to follow this procedure will result in a memory leak and an eventual system crash The maximum length is 16 megabytes 16777216 bytes The data buffer can receive data valu...

Page 64: ...operating system Failure to follow this procedure will result in a memory leak and an eventual system crash The maximum length is 16 megabytes 16777216 bytes The data buffer can receive data values o...

Page 65: ...ction call transaction A BYTE transaction identifier returned by QuickUsbReadDataAsync or QuickUsbWriteDataAsync immediate A BYTE value If nonzero the driver will not wait the default timeout value fo...

Page 66: ...QuickUsbOpen address A BYTE containing the port address Ports are addressed 0 to 4 corresponding to port A E data A PBYTE to a BYTE in which to place the data direction bit values Each bit in data cor...

Page 67: ...m length is 64 bytes Returns A non zero value if successful 0 otherwise Also returns the read value in value if successful Otherwise value is not modified Notes None QuickUsbWritePort Purpose None Par...

Page 68: ...independently Parameters hDevice A HANDLE that was returned from a call to QuickUsbOpen baudRate An unsigned long integer 32 bits containing the baud rate in bits per second Returns A non zero value i...

Page 69: ...port Parameters hDevice A HANDLE that was returned from a call to QuickUsbOpen portNum The serial port number Serial port 0 P1 0 serial port 1 P2 1 data A pointer to a buffer in which to place the dat...

Page 70: ...ial port Parameters hDevice A HANDLE that was returned from a call to QuickUsbOpen portNum The serial port number Serial port 0 P1 0 serial port 1 P2 1 data A pointer to a buffer containing the data l...

Page 71: ...inter to a buffer in which to place the data length The length of the data buffer in bytes The maximum length is 64 bytes Returns A non zero value if successful 0 otherwise In addition length is set t...

Page 72: ...d from data A pointer to a buffer in which to place the received data length A pointer to the number of bytes to read The maximum length is 64 bytes Returns A non zero value if successful 0 otherwise...

Page 73: ...e the received data length The number of bytes to send and receive The maximum length is 64 bytes Returns A non zero value if successful 0 otherwise In addition the data buffer is filled with the rece...

Page 74: ...ynchronous slave FIFO 17 I O Model simple 7 I O Models master mode 6 I O Pins unused 4 IFCLK 5 interpacket delay 2 interrupt 1 latency 2 master 1 mode GPIF master 5 OE5 pipe 1 Power 3 power supply ext...

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