Designing Hardware for QuickUSB
Slave FIFO I/O Models
The HSPP may also be operated in ‘Slave FIFO’ mode. In this mode, the GPIF
programmable DMA engine is disabled and the QuickUSB FIFOs are controlled
directly by external logic signals. GPIF master mode command/data transfers
are not applicable in slave FIFO mode since the GPIF programmable DMA
engine is disabled. Slave FIFO mode is selected by changing Bits1-0 of the
SETTING_FIFO_CONFIG setting and may be changed at any time. In slave FIFO
mode, data is transferred to and from the QuickUSB FIFOs using the standard
(EP6) &
(EP2) functions. These
endpoints are double-buffered by default. The QuickUSB module can be
configured to perform slave FIFO transfers in either synchronously or
asynchronously by changing Bit 3 of the
setting. The
slave FIFO flags may be queried using the
The following signals are required for slave mode operation:
Pin Name
Alternate
Name
Description
Default Config
IFCLK
IFCLK
Clock for synchronous I/O
Rising edge
FD[15:0] PD[7:0], PB[7:0] Bi-directional FIFO data bus
N/A
CTL0
FLAGA
Programmable level flag (Half-full)
Indexed mode
CTL1
FLAGB
FIFO Full Status Flag
Indexed mode
CTL2
FLAGC
FIFO Empty Status Flag
Indexed Mode
PA2
nSLOE
Enables the FD outputs for the selected
OUT FIFO
Synchronous,
Active low
RDY0
nSLRD
FIFO read enable/clock
Synchronous,
Active low
RDY1
nSLWR
FIFO write enable/clock
Synchronous,
Active low
PA6
nPKTEND
Indicates the end of a short IN packet
Synchronous,
Active low
PA7
nSLCS
FIFO Chip Select
Synchronous,
Active low
PA5:PA4 FIFOADR[1:0]
Selects the active FIFO for FD and flags.
00=EP2, 01=EP4,10=EP6, 11=EP8
N/A
Table 3 - Slave FIFO Mode I/O Connections
There are three Slave FIFO I/O Models available with QuickUSB. For Slave FIFO
Modes, no special firmware file is required. Simply use the Simple I/O Model
firmware file and program the
bit appropriately to
implement the desired I/O model.
16
High Speed Parallel Port
