Designing Hardware for QuickUSB
FIFO Handshake I/O Model
This I/O model is designed specifically to allow QuickUSB to connect directly to
external synchronous or asynchronous FIFOs. This I/O model is ideal for
applications that combine QuickUSB with an FPGA. The
QuickUsbRead/WriteData functions read or write streaming data to FIFOs inside
the FPGA while the QuickUsbRead/WriteCommand functions control a register
array inside the FPGA to manage internal FPGA operations.
With this I/O model, you simply instantiate a FIFO in the FPGA and connect the
data and control lines to the QuickUSB module. Please note the FIFO timing
requirements given in the ‘Data Transfers’ section.
This I/O model is implemented in the QuickUSB firmware file
‘quickusb-fifohs vX.XX.qusb’ where X.XX is the firmware version number.
Command Transfers
IFCLK
IFCLK
Addr[N]
X
t
XGD
CMD_DATA
CTL0
REN
CTL1
WEN
CTL2
nREN
CTL3
nWEN
CTL4
nOE
CTL5
GPIFADR
GPIFADR
FD
PB, PD
Name
Pin
Z
Write Cycle
X
Z
nEMPTY
RDY0
nFULL
RDY1
X
X
t
IFCLK
t
XCTL
t
SGA
Signifies QuickUSB Write
to the Data Bus
t
XCTL
t
XCTL
Data[N]
IFCLK
IFCLK
Addr[N]
X
t
DAH
CMD_DATA
CTL0
REN
CTL1
WEN
CTL2
nREN
CTL3
nWEN
CTL4
nOE
CTL5
GPIFADR
GPIFADR
FD
PB, PD
Name
Pin
Z
Data[N]
Read Cycle
X
Z
nEMPTY
RDY0
nFULL
RDY1
X
X
t
IFCLK
t
XCTL
t
SGD
t
SGA
Signifies QuickUSB Read
from the Data Bus
t
XCTL
t
XCTL
High Speed Parallel Port
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