BitFlow Cyton-CXP, Hardware Reference Manual

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Quadrature Encoder CON15 Register
Version A.0 BitFlow, Inc. CYT-5-7
QENC_INTRVL_
LL R/WR/W, CON15[23..0], Karbon, Neon
This register contains the lower limit value that is used to start acquisition when the
system is in interval mode (see QENC_INTRVL_MODE).
QENC_DECODE R/W, CON15[24], Karbon, Neon
This bit determines how often the quadrature counter is incremented.
QENC_AQ_DIR R/W, CON15[26..25], Karbon, Neon
This bit controls which quadrature encoder direction is used for acquisition.
QENC_INTRVL_
MODE R/W, CON15[27], Karbon, Neon
When this bit is 1, interval mode is turned on. When interval mode is on, lines are only
captured when the encoder counter is between the lower limit (set by QENC_
INTRVL_LL) and the upper limit (set by QENT_INTRVL_UL). If the counter is outside of
this range, lines are not acquired. Whether lines are acquired as the counter incre-
ments through the interval, or decrements through the interval, or in both directions
are controlled by QENC_AQ_DIR.
QENC_NO_
REAQ R/W, CON15[28], Karbon, Neon
This bit controls how the quadrature encoder system handles the situation where the
encoder does not smoothly increase (or decrease if QENC_AQ_DIR = 1). If there is
“jitter” in the encoder signal, often caused by problems with the mechanical systems,
it is possible for the board to acquire the same line or lines more than once as the
QENC_DECODE Meaning
0 Counter increments on the rising edge of input A
and the rising edge of input B. This is also called “2x”
modes.
1 Counter increments on both the rising and falling
edge of A and both the rising and falling edge of B.
This is also called “4x” mode.
QENC_AQ_DIR Meaning
0 (00b) Lines are acquired in both directions
1 (01b) Lines are acquired only in the positive direction.
2 (10b) Lines are acquired only in the negative direction.
3 (11b) Reserved