BitFlow Cyton-CXP, Hardware Reference Manual

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Karbon/Cyton-CXP I/O System Registers CON60
Version A.0 BitFlow, Inc. CYT-7-3
RD_BOX_IN_TTL RO, CON60[11..0], Karbon-CXP, Cyton-CXP
These bits reflect the real-time state of the 12 TTL inputs on the IO Box.
RD_BOX_IN_DIF RO, CON60[23..12], Karbon-CXP, Cyton-CXP
These bits reflect the real-time state of the 12 differential inputs on the IO Box.
ENINT_CXP R/W, CON60[24], Karbon-CXP, Cyton-CXP
This bit enables interrupts from the CXP subsystem.
INT_CXP RO, CON60[25], Karbon-CXP, Cyton-CXP
This bit indicates the existence of an interrupt from the CXP subsystem. The individual
interrupt must be cleared in the CXP subsystem in order for this bit to reset.
SW_TRIG R/W, CON60[29], Karbon-CXP, Cyton-CXP
Writing the bit to 1 causes the internal trigger signal to be asserted. Writing it to a 0
will de-assert the internal trigger signal.
SW_ENCA R/W, CON60[30], Karbon-CXP, Cyton-CXP
Writing the bit to 1 causes the internal encoder A signal to be asserted. Writing it to a
0 will de-assert the internal encoder A signal.
SW_ENCB R/W, CON60[31], Karbon-CXP, Cyton-CXP
Writing the bit to 1 causes the internal encoder B signal to be asserted. Writing it to a
0 will de-assert the internal encoder B signal.