BitFlow Cyton-CXP, Hardware Reference Manual

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General Description and Architecture General Description
Version A.0 BitFlow, Inc. CYT-1-7
camera. Trigger packets work in a similar manner, the trigger packet is a destination
for the board’s I/O system, and any number of sources can be routed to the CXP trig-
ger.
1.3.5 Cyton-CXP I/O system
The Cyton-CXP has a sophisticated I/O system, which is extremely flexible. The system
take in many inputs, routes them to a number of internal signals which can be further
manipulate, then routes the results to a wide rand of outputs. The I/O system is dis-
cuss in more detail in Section 7.1.
1.3.6 The Timing Sequencer Signal Generator
With the introduction of the Cyton-CXP, BitFlow is introducing a new signal generator,
the Timing Sequencer. The Timing Sequencer (TS) is more flexible and more power
than the timing generators used on early BitFlow frame grabbers. It has the ability to
output multiple different size pulses, each of which can free-run or require a trigger.
The TS is more accurate than the NTG and has a finer granularity. The TS can also be
changed on the fly, with switch overs to the new timing exactly synchronized. See sec-
tion 4.1 for more information.
1.3.7 The Volume Of Interest Acquisition Engine
The Cyton-CXP introduces the concept of Volume of Interest (VOI) as part of its
StreamSync Acquisition Engine. This has been designed from the ground up to satisfy
the needs of real world machine vision application. The VOI provide robust and flexi-
ble programming that can handle of a wide variety of pixel, line, frame and sequence
acquisition commands either manually from software control, or externally via hard-
ware triggers. There is fully support for X and Y offsets, X and Y Region of interests,
sequences and sequences of sequences. See section 2.2 for more information.
1.3.8 The StreamSync System
The Cyton-CXP has a brand new, designed from scratch acquisition and DMA engine
called the StreamSync system. The StreamSync system has been designed to opti-
mize acquisition and DMA throughput over the PCIe bus given a wider variety of
internal PC conditions. In addition, the Stream Sync system has been designed to
automatically resync and recover should there every be packet lost (either on the
input or the output side of the board), resulting in much more usable and fault toler-
ant image sequences in host memory. For more information see Section 2.1 and Sec-
tion 3.1.