Product Specifications and
Operations Manual
ELT160.60.100-07NC
Transparent Matrix Display
Beneq Oy
Olarinluoma 9
Tel. +358 9 7599 530
VAT ID FI25115461
FI-02200 Espoo
Fax +358 9 7599 5310
www.beneq.com
Finland
www.lumineq.com
Date: October 7, 2019
Document number: ED001129C
Page | 9
Table 3. J1 connector pinouts
PIN #
Symbol
Purpose
1
VH
+12V Power
2
VH
+12V Power
3
GND
Ground
4
GND
Ground
5
SCLK
SPI Clock from Master
6
MOSI
SPI Master Out Slave In
7
SS
SPI Slave Select
8
Reserved
Do not connect
9
SELFTEST Self Test Input
10
LUMA
Analog dimming
3.4
Interface information and Protocol
Beneq EL160.60.100-07NC display incorporates an SPI interface that is similar to many LCD
modules. This SPI video interface provides a low-cost, flexible method for controlling display
brightness and power consumption. Designers should select the chip set or embedded board
that best suits their particular architecture.
3.4.1
Video Input signals
The SPI is driven with the rising edge of SCLK. A falling edge on SS signal indicates the
beginning of an access on the SPI, the rising edge of SS signal ends an access on SPI. An
access must consist of exactly 8 bits for write operation.
The SPI interface Clock polarity (CPOL) and clock phase (CPHA) are 0. At CPOL=0 the base
value of the clock is zero for CPHA=0 and data are captured on the clock's rising edge (low to
high transition) and data is propagated on a falling edge (high to low clock transition).
The timing restrictions on SPI are defined in figure 2 and table 4:
