BECKWITH ELECTRIC M-0420, Instruction Book

Page: 151 / 174

A–3
Theory of Operation – Appendix A
The output of the PGA, representing in time se-
quence the eleven measured parameters, is scaled
to make it compatible with the ADC. Each of the
inputs occupies the ADC 16 times per cycle,
meaning that 12-bit resolution of eleven indepen-
dent quantities must be determined every 1.042
ms.
Since available chips designed for efficient digi-
tal signal processing are not well suited to the
overhead tasks of the relay, these functions are
assigned to a second, or “host,” microprocessor
which is much better suited to the purpose. The
host processor performs all overhead functions,
e.g., monitors the keyboard for operator requests,
updates memories for setpoint values, facilitates
operator interaction via a 2-line-by-24-character
liquid crystal display, establishes two-way com-
munication using the RS-232C serial ports, and
ultimately analyzes the data from the DSP to
determine the need for a trip command.
A.3 Discrete Fourier Transform
The digital signal processor makes possible the
many calculations in the very limited time avail-
able. Fundamental to the relay are the rms val-
ue, frequency, and phase angle of the fundamental
frequency phasors. A DFT is executed in order
to estimate these parameters while filtering the
dc offset and harmonics from the fundamental.
The use of an algorithm based on the DFT to
compute the frequency and to determine the phase-
angle for real/reactive power measurements has
several advantages over the approach used in
other commercially available digital frequency
relays. Relays that calculate these values by
measuring the time duration between the two
successive zero crossings of the system voltage
can be adversely affected by harmonic distortion
and noise, which can shift the zero crossings or
create multiple zero crossings. The algorithm used
in the M-0420 Multifunction Relay uses voltage
phasor estimates obtained from the DFT to
compute the frequency. This algorithm not only
provides very reliable frequency estimates, but
since the DFT rejects dc and harmonic components
in the signal, the frequency estimates are not
affected by these components. Additionally,
deriving the positive sequence voltage phasor
from the DFT means that the frequency function
will continue to operate should any single- or
two-phase fault occur.
To describe the DFT, assume the analog inputs
are sinusoidal signals corrupted by noise. The
following mathematical notation will be used:
z(t) = The instantaneous value of a voltage
or a current signal
z
k
= The sampled value of signal z(t) at
k-th instant
ω
o
= The fundamental power system fre-
quency in radians per second
T = The interval between two samples,
i.e., z
k
= z (kT)
N = The number of samples in one cycle
of fundamental frequency
The computation of real (Zr
k
) and imaginary (Zi
k
)
components of the complex phasor (Z) are as
follows:
Z
i
k
= 2
N
Σ
Z
k-r
sin
N-1
r=0
2
π
r
N
Z
r
k
= 2
N
Σ
Z
k-r
cos
N-1
r=0
2
π
r
N
(1)
where z
–1
, z
–2
, ...z
–(N–1)
are set to zero.
A major obstacle to the direct computation of
(Z
r
k
) and (Z
i
k
) is that 2N multiplications are re-
quired at each sample. The above equations can
be rewritten in recursive form to ease the com-
putation:
Z
r
k
= Z
r
k-1
+
2
N
(Z
k
- Z
k-N)
cos 2
π
k
N
Z
i
k
= Z
i
k-1
+
2
N
(Z
k
- Z
k-N)
sin 2
π
k
N
(2)
where z
–1
, z
–2
, ...z
–N
and Z
r
–1
, Z
i
–1
are set to
zero, and only two multiplications are required
per sample. Also, the use of (2) results in a
stationary phasor in contrast to the use of (8)
which would result in a rotating phasor.
The magnitude |Z| and phase angle (
θ
) of the
phasor can be obtained as follows:
|Z| =
S
Z
2
r
+ Z
2
i
and
θ
= tan
–1
(Z
i
/Z
r
) (3)