Beckhoff FC3101, Documentation

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FC310x as master
FC3101 and FC3102 18 Version: 3.0
Fig. 13: Normal DP cycle for Stay in Data Exch (for WD time)
first faulty and subsequent DP cycles in the "Stay in Data-Exch (for WD-Time)" mode (slave 3 does
not respond)
Fig. 14: First faulty and subsequent DP cycles for Stay in Data Exch (for WD time)
Changes of the slave's input data if the slave does not respond correctly
Here you can specify whether the input data of the slave are set to 0 if the slave fails ("Inputs will be set to
0", default setting) or whether the old value should be retained ("No changes"). In either case the
DpState
[
}
25] of the slave is set to value other than 0, so that the task can always recognize whether or not the data
is valid. If a slave gives a faulty answer, the input data is always set to 0, independently of the setting of
Changes of the Input Data .
Setting the slave's restart behavior if the DP connection to the slave is removed
This specifies whether the DP connection to slave whose DP connection has been removed is automatically
re-established, or whether this should be done manually as a result of a call to ADS-WriteControl (see
ADS-
Interface [
}
28] ).
The reaction of the master if the DP connection to the slave is removed
This specifies whether removing the DP connection to a slave has no other effects (No Reaction, the default
setting), or whether the master should enter the STOP state, thus removing the DP connections to all the
slaves.
Effect on the state of the master (Clear mode), if the DP connection to the slave is removed
Clear mode (TwinCAT 2.8: see PROFIBUS [
}
42] tab of the master, TwinCAT 2.9: see Fault Settings [
}
51]
dialog) can be used to specify that the master should switch to or remain in "Clear" state, as long as at least
one MC slave (setting: "Only MC slaves") or any slave (setting: "All slaves") does not respond correctly (i.e.
has a
DpState [ } 25] not equal 0).
The Reaction of the Master setting (see the slave's Features [ } 59] tab), which was described in the
previous chapter, has priority over the Auto-Clear mode , so that when an appropriately set slave fails, the
Master enters the STOP state.
Failure of the master
Monitoring in the PLC/IO task
In the event of persistent bus faults, the DP cycle also may extend up to 100 ms, even with 12 Mbit/s. In
order to monitor the DP master, there is a status variable CycleCounter, and this can be linked in the PLC
(see the
Master Diagnostics [
}
20] chapter). This variable is incremented by the master after each DP cycle,
so that failure of the master can be detected by monitoring this variable in the PLC.