Basics communication
EK1110, EK1110-0008
19
Version: 2.
Safe-Operational (Safe-Op)
During transition between
Pre-Op
and
Safe-Op
the EtherCAT slave checks whether the sync manager
channels for process data communication and, if required, the distributed clocks settings are correct. Before
it acknowledges the change of state, the EtherCAT slave copies current input data into the associated DP-
RAM areas of the EtherCAT slave controller (ECSC).
In
Safe-Op
state mailbox and process data communication is possible, although the slave keeps its outputs
in a safe state, while the input data are updated cyclically.
Note
Outputs in SAFEOP state
The default set watchdog monitoring sets the outputs of the module in a safe state - de-
pending on the settings in SAFEOP and OP - e.g. in OFF state. If this is prevented by de-
activation of the watchdog monitoring in the module, the outputs can be switched or set
also in the SAFEOP state.
Operational (Op)
Before the EtherCAT master switches the EtherCAT slave from
Safe-Op
to
Op
it must transfer valid output
data.
In the
Op
state the slave copies the output data of the masters to its outputs. Process data and mailbox
communication is possible.
Boot
In the
Boot
state the slave firmware can be updated. The
Boot
state can only be reached via the
Init
state.
In the
Boot
state mailbox communication via the
file access over EtherCAT
(FoE) protocol is possible, but no
other mailbox communication and no process data communication.
3.5
CoE - Interface: notes
This device has no CoE.
Detailed information on the CoE interface can be found in the
EtherCAT system documentation
on the
Beckhoff website.
3.6
Distributed Clock
The distributed clock represents a local clock in the EtherCAT slave controller (ESC) with the following
characteristics:
• Unit
1 ns
• Zero point
1.1.2000 00:00
• Size
64 bit
(sufficient for the next 584 years; however, some EtherCAT slaves only offer 32-bit support,
i.e. the variable overflows after approx. 4.2 seconds)
• The EtherCAT master automatically synchronizes the local clock with the master clock in the EtherCAT
bus with a precision of < 100 ns.
For detailed information please refer to the
EtherCAT system description
.
