Axiom SBC8156, User Manual

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SBC8156 Pentium All-in-One CPU Card Series User’s Manual
Award BIOS Utility &*
z
DRAM Enhanced Paging
When Enabled, the chipset keeps the page open until a page/row miss.
When Disabled, the chipset uses additional information to keep the
DRAM page open when the host may be "right back." The default value
is
“Enabled” .
z Fast MA to RAS# Delay CLK
The values in this field are set by the system board designer,
depending on the DRAM installed. Do not change the values in this
field unless you change the specifications of installed DRAM or the
installed CPU. The default value is
“2 Clks” .
z System BIOS Cacheable
Selecting Enabled allows caching of the system BIOS ROM at F0000h-
FFFFFh, resulting in better system performance. However, if any
program writes to this memory area, a system error may result. The
default value is
“Disabled” .
z
Video BIOS Cacheable
Selecting Enabled allows caching of the video BIOS ROM at C0000h to
C7FFFh, resulting in better video performance. However, if any
program writes to this memory area, a system error may result. The
default value is
“Disabled” .
z 8/16 Bit I/O Recovery Time
The I/O recovery mechanism adds bus clock cycles between PCI-
originated I/O cycles to the ISA bus. This delay takes place because
the PCI bus is so much faster than the ISA bus.
These two fields let you add recovery time (in bus clock cycles) for 16-
bit and 8-bit I/O. The default values are “1” for 8 Bit I/O Recovery Time
and “2” for 16 Bit I/O Recovery Time.
z
Memory Hole at 15M-16M
You can reserve this area of system memory for ISA adapter ROM.
When this area is reserved, it cannot be cached. The user information
of peripherals that need to use this area of system memory usually
discusses their memory requirements. The default value is
“Disabled” .
z PCI 2.1 Compliance
Concurrent PCI allows multiple PCI transfers from the PCI master
buses to memory to CPU. By default, this field is set to
Disabled .