Avnet Qorvo, Hardware User'S Manual

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Page 2
Qorvo 1800MHz Small Cell RF Card Hardware User’s Guide
Contents
1 Document Control .................................................................................................3
2 Version History ......................................................................................................3
3 Introduction ...........................................................................................................4
3.1 Zynq Ult RFSoC Development Kit ............................................................................. 5
3.2 Glossary ................................................................................................................................... 6
3.3 Reference Documents ............................................................................................................. 7
4 Architecture and Features .....................................................................................8
4.1 List of Features ........................................................................................................................ 8
4.2 Block Diagram .......................................................................................................................... 9
5 Functional Description ......................................................................................... 10
5.1 ZCU111 Interface ................................................................................................................... 10
5.2 Digital Isolation ....................................................................................................................... 11
5.3 Power Options........................................................................................................................ 12
5.4 Attenuators Digital Step Attenuator (DSA) DevicesControl Interfaces .................................. 13
5.4.1 Parallel DSA Control Interface ....................................................................................... 13
5.4.2 Serial DSA Control Interface .......................................................................................... 13
5.5 Rebuilding the Reference Design .......................................................................................... 16
5.6 SPI Controller ......................................................................................................................... 17
5.7 GPIO Assignments ................................................................................................................ 18
5.8 EEPROM and I2C Interface ................................................................................................... 20
5.9 Digital Test Pins ..................................................................................................................... 21
5.10 Status LEDs ........................................................................................................................... 23
5.11 RFMC Connector Pin Assignments ....................................................................................... 24
5.12 Pi Pad Attenuators ................................................................................................................. 29
5.13 ADC Input Protection ............................................................................................................. 30
5.13.1 RX-side ADC Over-voltage Protection ........................................................................... 30
Rx LNA Bypass Mechanisms ........................................................................................................ 31
5.14 Directional Coupler ................................................................................................................ 32
5.15 Circulator ................................................................................................................................ 32
6 Regulatory and Compliance Information ............................................................. 33
7 Getting Help and Support .................................................................................... 34
8 Appendix A
– Alternate Reverse Build Variant .................................................... 35