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Qorvo 1800MHz Small Cell RF Card Hardware User’s Guide
Hardware User’s Guide
The programmable logic and software in the Avnet reference design implements the serial protocol
for these attenuators. See 5.5.
The image below shows data being clocked out to one of the attenuators on the Channel 1 serial
bus. The serial clock here is 5MHz. The first signal, LE, is the latch enable signal, which toggles
after the serial data in (SI) has been clocked in.
Figure 11
– Scope Capture of SAM signals for Writing to an Attenuator
