Avnet COM Express MSC C6B-SLH User Manual Download Page 105

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MSC C6B-SLH

MSC C6B-SLH User Manual

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Feature

Options

Description

L1 Substates

L1.1 & L1.2, L1.1, L1.2,
Disabled

PCI Express L1 Substates settings

Gen3 Eq Phase3 Method

Software Search, Hardware,
Static Coeff.

PCIe Gen3 Equalization Phase 3 Method

UPTP

Enabled, Disabled

Upstream Port Transmitter Preset

DPTP

Enabled, Disabled

Downstream Port Transmitter Preset

ACS

Enabled, Disabled

Enable/Disable Access Control Service Extended Capabilty.

URR

Enabled, Disabled

Enable or disable PCI Express Unsupported Request Reporting.

FER

Enabled, Disabled

Enable or disable PCI Express Device Fatal Error Reporting.

NFER

Enabled, Disabled

Enable or disable PCI Express Device Non-Fatal Error Reporting.

CER

Enabled, Disabled

Enable or disable PCI Express Device Correctable Error Reporting.

CTO

Enabled, Disabled

Enable or disable PCI Express Completion Timer TO.

SEFE

Enabled, Disabled

Enable or disable Root PCI Express System Error on Fatal Error.

SENFE

Enabled, Disabled

Enable or disable Root PCI Express System Error on Non-Fatal
Error.

SECE

Enabled, Disabled

Enable or disable Root PCI Express System Error on Correctable
Error.

PME SCI

Enabled, Disabled

Enable or disable PCI Express PME SCI.

Hot Plug

Enabled, Disabled

Enable or disable PCI Express Hot Plug.

Advanced Error Reporting

Enabled, Disabled

Advanced Error Reporting Enable/Disable.

PCIe Speed

Gen1, Gen2, GEN 3

Select PCI Express port Speed

Transmitter Half Swing

Enabled, Disabled

Transmitter Half Swing Enable/Disable

Detect Timeout

Value

The number of milliseconds reference code will wait for link to exit
Detect state for enabled ports before assuming there is no device
and potentially disabling the port.

Extra Bus Reserved

0-7

Extra Bus Reserved (0-7) for bridges behind this Root Bridge.

Reserved Memory

1-20MB

Reserved Memory and Prefetchable Memory (1-20MB) Range for
this Root Bridge.

Summary of Contents for COM Express MSC C6B-SLH

Page 1: ...COM Express Basic Module MSC C6B SLH Type 6 Pinout 6th Generation Intel CoreTM Processor Family Intel 100 Series Chipset Rev 1 1 2021 04 29 User Manual ...

Page 2: ... for any particular purpose is implied The information in this document is provided as is and is subject to change without notice EMC Rules This unit has to be installed in a shielded housing If not installed in a properly shielded enclosure and used in accordance with the instruction manual this product may cause radio interference in which case the user may be required to take adequate measures ...

Page 3: ... contacting Avnet Integrated MSC Technical Support please consult the respective pages on our web site at www msc technologies eu for the latest documentation drivers and software downloads If the information provided there does not solve your problem please contact our Avnet Integrated MSC Technical Support Phone 49 8165 906 200 Email support boards avnet eu ...

Page 4: ...s 31 2 13 9 LVDS eDP 32 2 13 10 Digital Display Interfaces 35 2 13 11 Serial Interface Signals 38 2 13 12 Miscellaneous 38 2 13 13 Power and System Management 39 2 13 14 General Purpose I O 40 2 13 15 SPI Interface 41 2 13 16 Module Type Definition 42 2 13 17 Power and GND 43 2 14 Pin List 44 3 Jumpers and Connectors 50 3 1 Jumpers 50 3 2 Fan Connector 51 4 Watchdog 51 5 System Resources 52 5 1 PC...

Page 5: ...7 6 8 37 EC Hardware Monitoring 88 6 8 38 Module specific Initialization 92 6 8 39 Onboard GPIO Initialization 93 6 9 Chipset 95 6 9 1 System Agent Configuration 95 6 9 2 Memory Configuration 96 6 9 3 Graphics Configuration 98 6 9 4 PEG Port Configuration 99 6 9 5 PCH IO Configuration 101 6 9 6 PCI Express Configuration 103 6 9 7 PCIE GEN3 Eq Parameters 104 6 9 8 PCIe Root Port x 104 6 9 9 SATA In...

Page 6: ...MSC C6B SLH MSC C6B SLH User Manual 6 144 Revision History Rev Date Description 1 0 2021 03 09 First Release 1 1 2021 04 29 Updated Bios chapter legacy Raid not supported anymore ...

Page 7: ...0r3b pdf http www t13 org 4 Serial ATA Specification Serial ATA 1 0 gold pdf Last update August 29th 2002 Rev 1 0 http www sata io org 5 IEEE Std 802 3 2002 802 3 2002 pdf http www ieee org 6 VESA Embedded DisplayPort Standard eDP_v1_3 mem pdf Last update 13 01 2012 http www vesa org 7 Universal Bus Specification usb_20 pdf Last update April 27th 2000 http www usb org 8 Universal Serial Bus Revisi...

Page 8: ...cates a hazardous situation that if not avoided will result in death or serious injury Warning Indicates a hazardous situation that if not avoided could result in death or serious injury Caution Indicates a hazardous situation that if not avoided could result in minor or moderate injury All safety messages have a safety alert symbol and are structured as follows Danger Warning or Caution Type of h...

Page 9: ...ces as described herein 1 5 Non Intended Use NOTE Use the COM Express module in the specified temperature ranges only NOTE Use the COM Express module in the specified humidity ranges only NOTE Use the COM Express module under Intel specified use conditions only 1 6 Electrostatic Sensitive Device The MSC COM Express module is an electrostatic sensitive device It is packed accordingly NOTE Handle th...

Page 10: ...nd development motherboards providing the interface infrastructure for the COM Express module using PC type connectors for external access Currently four module sizes are defined in the COM Express Specification 2 1 the Mini Module the Compact Module the Basic Module and the Extended Module The main difference between them is the over all physical size and the performance envelope supported All mo...

Page 11: ...B SLH MSC C6B SLH User Manual 11 144 2 2 Module Photos Top Side View 1 Top side memory socket 2 MAC address label 3 Layout revision 4 Board Identification number BID 5 Fan connector 6 CPU 7 PCH 6 7 1 2 5 4 3 ...

Page 12: ...MSC C6B SLH MSC C6B SLH User Manual 12 144 Bottom Side View 8 Bottom side memory socket 9 COM Express connector 10 BIOS label 11 Board identification label 8 10 9 11 ...

Page 13: ...x Eight PCI Express 3 0 lanes PEG x16 port Support pins for two Express Cards Display interfaces o three independent display controllers o Digital Display Interface DDI configurable as HDMI DVI or Display Port o Dual 24 bit LVDS channel shared with eDP High definition digital audio interface external CODEC Single GBit Ethernet interface Intel Ethernet Controller I219 LM LPC interface Two high spee...

Page 14: ...MSC C6B SLH MSC C6B SLH User Manual 14 144 2 4 Block Diagram ...

Page 15: ...Ports 1 2 0 2 2 HSUART Functionality based on the 16550 industry standards SIR mode dual clock and external read enable signal for RAM wake up when using external RAMs is not supported The UART 16550 8 bit Legacy mode only operates with PIO transactions DMA transactions are not supported in this mode A B CAN interface on SER1 0 1 0 A B SATA Ports 1 4 4 SATA 6 0 GBit s SATA Revision 3 x A B HDA Dig...

Page 16: ...Speaker Out 1 1 1 A B External BIOS ROM support 0 2 1 A B Reset Functions 1 1 1 Power Management A B Thermal Protection 0 1 0 A B Battery Low Alarm 0 1 1 A B Suspend 0 1 1 A B Wake 0 2 2 A B Power Button Support 1 1 1 A B Power Good 1 1 1 A B VCC_5V_SBY Contacts 4 4 4 A B Sleep Input 0 1 1 A B Lid Input 0 1 1 A B Fan Control Signals 0 2 2 A B Trusted Platform Modules 0 1 1 TPM 1 2 module ...

Page 17: ...Smart Cache 2ch DDR4 Intel Xeon Processor E3 1535M v5 QC 2 90GHz 3 80GHz 8MB Intel Smart Cache 2ch DDR4 TJUNCTION 100 C Chipset Mobile Intel HM170 QM170 or CM236 Chipset optional ECC only with CM236 Memory Two 260 pin DDR4 SO DIMM sockets for up to two 16GB DDR4 modules Maximal height 1250mil 31 75mm PC4 1866 2133 DDR4 RS SDRAM DDR4 1866 2133 SATA 4 SATA channels up to 6 0 Gbit s SATA Revision 3 x...

Page 18: ...gnal for RAM wake up when using external RAMs is not supported The UART 16550 8 bit Legacy mode only operates with PIO transactions DMA transactions are not supported in this mode Watchdog Timer Embedded controller creates watchdog alert and system reset TPM TPM module TPM 1 2 SLB9660 Fan Supply 4 pin header for support of a 12V PWM fan Real Time Clock RTC integrated in CPU package CMOS Battery Ex...

Page 19: ...1 Running Mode All measurements were made by plugging the MSC C6B SLH module onto a MSC C6 MB EVA carrier The module was equipped with two 8GByte memory modules 8GB DDR4 2133 SODIMM M4SR 8GSSOC0G E The table below shows typical values which refer to consumption of the module itself without consumption of the base board and CPU fan The following applications have been tested with minimum 15 minutes...

Page 20: ... 1 W 20 6 W C6B SLH 025 Intel CoreTM i5 6442EQ QC 1 90GHz 2 70GHz 25W 6MB Intel Smart Cache 2ch DDR4 PCH QM170 5 5 W 29 5 W 42 1 W 25 2 W C6B SLH 006 Intel CoreTM i5 6440EQ QC 2 70GHz 3 40GHz 45W 6MB Intel Smart Cache 2ch DDR4 PCH QM170 5 5 W 51 5 W 65 4 W 32 8 W C6B SLH 008 Intel CoreTM i7 6820EQ QC 2 80GHz 3 50GHz 45W 8MB Intel Smart Cache 2ch DDR4 PCH QM170 5 7 W 50 3 W 66 5 W 40 8 W C6B SLH 00...

Page 21: ...C6B SLH 003 Intel CoreTM i3 6102E DC 1 90GHz 25W 3MB Intel Smart Cache 2ch DDR4 PCH HM170 5V_SBY 0 77 W 0 49 W C6B SLH 104 Intel CoreTM i3 6100E DC 2 70GHz 35W 3MB Intel Smart Cache 2ch DDR4 PCH CM236 5V_SBY 0 82 W 0 54 W C6B SLH 025 Intel CoreTM i5 6442EQ QC 1 90GHz 2 70GHz 25W 6MB Intel Smart Cache 2ch DDR4 PCH QM170 5V_SBY 0 76 W 0 48 W C6B SLH 006 Intel CoreTM i5 6440EQ QC 2 70GHz 3 40GHz 45W ...

Page 22: ...CPU module provides two sockets for memory modules which have to meet the following demands 260 pin unbuffered DDR4 SO DIMM 1 2V Supply Voltage PC4 1866 2133 DDR4 RS SDRAM DDR4 1866 2133 Maximum module height 1250mil 31 75mm SPD Serial Presence Detect EEPROM Max 16GB per socket ...

Page 23: ...6B SLH User Manual 23 144 2 10 Mechanical Dimensions 2 10 1 Basic Module There are two height options defined in the COM Express specification 5mm and 8mm The height option is defined by the connectors on the baseboard ...

Page 24: ...ems There must be a cooling solution for the system The surface temperature of the heat spreader should not exceed 80 C Main issue for the thermal functionality of a system is that each device of the module is operated within its specified thermal values The max value for the CPU is 100 C T die So there may be system implementations where the heat spreader temperature could be higher Anyway in thi...

Page 25: ...nce may be different For example the PCI group is defined as having a 3 3V power rail meaning that the output signals will only be driven to 3 3V but the pins are tolerant of 5V signals An additional label Sus indicates that the pin is active during suspend states S3 S4 S5 If suspend modes are used then care must be taken to avoid loading signals that are active during suspend to avoid excessive s...

Page 26: ...l Pin Type Signal Level Power Rail Remark Tolerance PU PD SR Description Source Target GBE0_MDI 0 3 GBE0_MDI 0 3 I O Analog 3 3V Sus 3 3V Gigabit Ethernet Controller 0 Media Dependent Interface Differential Pairs 0 1 2 3 The MDI can operate in 1000 100 and 10 Mbit sec modes MDI 0 B1_DA MDI 1 B1_DB MDI 2 B1_DC MDI 3 B1_DD Intel I219 LM GBE0_ACT OD CMOS 3 3V Sus 5V 20 mA Gigabit Ethernet Controller ...

Page 27: ..._TX SATA2_TX O SATA 1 0V AC coupled on module Serial ATA Channel 2 transmit differential pair PCH SATA2_RX SATA2_RX I SATA 1 0V AC coupled on module Serial ATA Channel 2 receive differential pair PCH SATA3_TX SATA3_TX O SATA 1 0V AC coupled on module Serial ATA Channel 3 transmit differential pair PCH SATA3_RX SATA3_RX I SATA 1 0V AC coupled on module Serial ATA Channel 3 receive differential pair...

Page 28: ...ngth on the carrier board Number of vias used on the carrier board PCB material and specification used for the carrier board Target device 2 13 5 PCI Express x16 Graphic Lanes Signal Pin Type Signal Level Power Rail Remark Tolerance PU PD SR Description Source Target PEG_TX 0 15 PEG_TX 0 15 O PCIe 3 3V AC coupled on module PCI Express Graphics transmit differential pairs These signals can also be ...

Page 29: ...PD Description Source Target EXCD 0 _CPPE I CMOS 3 3V 3 3V ePU 10 KΩ ExpressCard card request active low PCH EXCD 1 _CPPE I CMOS 3 3V 3 3V ePU 10 KΩ ExpressCard card request active low PCH EXCD 0 _RST O CMOS 3 3V 3 3V ePU 10 KΩ ExpressCard reset active low PCH EXCD 1 _RST O CMOS 3 3V 3 3V ePU 10 KΩ ExpressCard reset active low PCH ...

Page 30: ... ePU 10 KΩ USB channels 4 and 5 over current sense A pull up for this line is present on the module An open drain driver from a USB current monitor on the Carrier Board may drive this line low Do not pull this line high on the Carrier Board PCH USB_6_7_OC I CMOS 3 3V Sus 3 3V ePU 10 KΩ USB channels 6 and 7 over current sense A pull up for this line is present on the module An open drain driver fro...

Page 31: ...tiplexed address command and data bus PCH LPC_FRAME O CMOS 3 3V LPC frame indicates the start of an LPC cycle PCH LPC_DRQ0 I CMOS 3 3V 3 3V LPC serial DMA request not available PCH LPC_DRQ1 I CMOS 3 3V 3 3V LPC serial DMA request not available PCH LPC_SERIRQ I OD CMOS 3 3V 3 3V ePU 10 KΩ LPC serial interrupt PCH LPC_CLK O CMOS 3 3V eSR 33 Ω LPC clock output 33MHz nominal functional strap option PC...

Page 32: ...S_A0 A71 eDP_TX2 LVDS_A0 A72 eDP_TX2 LVDS_A1 A73 eDP_TX1 LVDS_A1 A74 eDP_TX1 LVDS_A2 A75 eDP_TX0 LVDS_A2 A76 eDP_TX0 LVDS_A_CK A81 eDP_TX3 LVDS_A_CK A82 eDP_TX3 LVDS_VDD_EN A77 eDP_VDD_EN LVDS_BKLT_EN B79 eDP_BKLT_EN LVDS_BKLT_CTRL B83 eDP_BKLT_CTRL LVDS_I2C_CK A83 eDP_AUX LVDS_I2C_DAT A84 eDP_AUX RSVD A87 eDP_HPD ...

Page 33: ...ifferential clock ANX1122 LVDS_B 0 3 LVDS_B 0 3 O LVDS LVDS Channel B differential pairs ANX1122 LVDS_B_CK LVDS_B_CK O LVDS LVDS Channel B differential clock ANX1122 LVDS_VDD_EN O CMOS 3 3V LVDS panel power enable ANX1122 LVDS_BKLT_EN O CMOS 3 3V LVDS panel backlight enable Board Controller LVDS_BKLT_CTRL O CMOS 3 3V LVDS panel backlight brightness control Board Controller LVDS_I2C_CK O CMOS 3 3V ...

Page 34: ...Ie AC coupled off module eDP differential pairs CPU eDP_VDD_EN O CMOS 3 3V 3 3V eDP power enable CPU eDP_BKLT_EN O CMOS 3 3V 3 3V eDP backlight enable Board Controller eDP_BKLT_CTRL O CMOS 3 3V 3 3V eDP backlight brightness control Board Controller eDP_AUX I O PCIe AC coupled off module eDP_AUX CPU eDP_AUX I O PCIe AC coupled off module eDP_AUX CPU eDP_HPD I CMOS 3 3V 3 3V Detection of Hot Plug Un...

Page 35: ...DI1_CTRLCLK DATA_AUX DP1_AUX HDMI1_CTRLCLK DATA DDI1_DDC_AUX_SEL DDI2 DDI2_PAIR0 DP2_LANE0 TMDS2_DATA2 DDI2_PAIR1 DP2_LANE1 TMDS2_DATA1 DDI2_PAIR2 DP2_LANE2 TMDS2_DATA0 DDI2_PAIR3 DP2_LANE3 TMDS2_DATACLK DDI2_HPD DP2_HPD HDMI2_HPD DDI2_CTRLCLK DATA_AUX DP2_AUX HDMI2_CTRLCLK DATA DDI2_DDC_AUX_SEL DDI3 DDI3_PAIR0 DP3_LANE0 TMDS3_DATA2 DDI3_PAIR1 DP3_LANE1 TMDS3_DATA1 DDI3_PAIR2 DP3_LANE2 TMDS3_DATA0...

Page 36: ...ne 0 3 differential pairs CPU DP2_AUX DP2_AUX I O AC coupled on module ePD 100 KΩ ePU 100 KΩ DisplayPort Aux control channel differential pair CPU DP2_HPD I CMOS 3 3V 3 3V ePD 100 KΩ DisplayPort Hot Plug Detect CPU DDI2_DDC_AUX_SEL I CMOS 3 3V 3 3V ePD 1 MΩ If this input is floating the AUX pair is used for the DP AUX signals If pulled high the AUX pair contains the CTRLCLK and CTRLDATA signals Ca...

Page 37: ...ct CPU DDI1_DDC_AUX_SEL I CMOS 3 3V 3 3V ePD 1 MΩ Pull to 3 3V on the Carrier with 100k Ohm resistor to configure the DDI1_AUX pair as the DDC channel Carrier board logic circuit TMDS2_DATA 0 2 TMDS2_DATA 0 2 O TMDS AC coupled off module HDMI DVI TMDS Data 0 3 output differential pairs CPU TMDS2_DATACLK TMDS2_DATACLK O TMDS AC coupled off module HDMI DVI TMDS Clock differential pairs CPU HDMI2_CTR...

Page 38: ...I2C_DAT I O CMOS 3 3V Sus 3 3V ePU 2 2 KΩ General purpose I2C port data I O line PCH SPKR O CMOS 3 3V 3 3V 4mA Output for audio enunciator the speaker in PC AT systems PCH BIOS_DIS 1 I CMOS 3 3V ePU 10 KΩ Module BIOS disable input Carrier board logic circuit BIOS_DIS 0 I CMOS 3 3V ePU 10 KΩ Module BIOS disable input Carrier board logic circuit WDT O CMOS 3 3V ePD 10 KΩ Active high output indicatin...

Page 39: ...imminent suspend operation used to notify LPC devices PCH SUS_S3 O CMOS 3 3V Sus 3 3V 24mA Indicates system is in Suspend to RAM state Active low output PCH SUS_S4 O CMOS 3 3V Sus 3 3V 24mA Indicates system is in Suspend to Disk state Active low output PCH SUS_S5 O CMOS 3 3V Sus 3 3V 0 5mA Ioh Indicates system is in Soft Off state Also known as PS_ON and can be used to control an ATX power supply ...

Page 40: ...r SMB_DAT I O OD CMOS 3 3V Sus 3 3V ePU 1 KΩ System Management Bus bidirectional data line Power sourced through 3 3V standby rail PCH Board Controller SMB_ALERT I CMOS 3 3V Sus 3 3V ePU 10 KΩ System Management Bus Alert active low input can be used to generate SMI System Management Interrupt or to wake the system Power sourced through 3 3V standby rail PCH Board Controller 2 13 14 General Purpose...

Page 41: ...wer 3 3V Sus Power supply for Carrier Board SPI sourced from Module nominally 3 3V The Module shall provide a minimum of 100mA on SPI_POWER Carriers shall use less than 100mA of SPI_POWER SPI_POWER shall only be used to power SPI devices on the Carrier BIOS_DIS 1 0 I CMOS 3 3V Sus 3 3V ePU 10 KΩ Selection straps to determine the BIOS boot device PCH Not supported Not recommended BIOS_DIS 1 0 SPI_C...

Page 42: ... TYPE pins and keeps power off e g deactivates the ATX_ON signal for an ATX power supply if an incompatible module pin out type is detected The Carrier Board logic may also implement a fault indicator such as a LED Carrier board logic TYPE10 O No connect on COM 0 Rev 2 1 Module Type 6 Dual use pin Indicates to the Carrier Board that a Type 10 Module is installed Indicates to the Carrier that a Rev...

Page 43: ...r input 5 0V 5 If VCC5_SBY is used all available VCC_5V_SBY pins on the connector s shall be used Only used for standby and suspend functions May be left unconnected if these functions are not used in the system design VCC3 3V SUS regulator VCC_RTC Power Real time clock circuit power input 3 0V 2 5V to 3 3V PCH GND Power Ground DC power and signal and AC signal return path All available GND connec...

Page 44: ...USB_SSRX1 D7 USB_SSTX1 A8 GBE0_LINK B8 LPC_DRQ0 C8 GND D8 GND A9 GBE0_MDI1 B9 LPC_DRQ1 C9 USB_SSRX2 D9 USB_SSTX2 A10 GBE0_MDI1 B10 LPC_CLK C10 USB_SSRX2 D10 USB_SSTX2 A11 GND FIXED B11 GND FIXED C11 GND FIXED D11 GND FIXED A12 GBE0_MDI0 B12 PWRBTN C12 USB_SSRX3 D12 USB_SSTX3 A13 GBE0_MDI0 B13 SMB_CK C13 USB_SSRX3 D13 USB_SSTX3 A14 GBE0_CTREF B14 SMB_DAT C14 GND D14 GND A15 SUS_S3 B15 SMB_ALERT C15...

Page 45: ...N2 C28 RSVD D28 RSVD A29 AC HDA_SYNC B29 AC HDA_SDIN1 C29 DDI1_PAIR5 D29 DDI1_PAIR1 A30 AC HDA_RST B30 AC HDA_SDIN0 C30 DDI1_PAIR5 D30 DDI1_PAIR1 A31 GND FIXED B31 GND FIXED C31 GND FIXED D31 GND FIXED A32 AC HDA_BITCLK B32 SPKR C32 DDI2_CTRLCLK_AUX D32 DDI1_PAIR2 A33 AC HDA_SDOUT B33 I2C_CK C33 DDI2_CTRLDATA_AUX D33 DDI1_PAIR2 A34 BIOS_DIS0 B34 I2C_DAT C34 DDI2_DDC_AUX_SEL D34 DDI1_DDC_AUX_SEL A3...

Page 46: ...SVD A49 EXCD0_CPPE B49 SYS_RESET C49 DDI3_PAIR3 D49 DDI2_PAIR3 A50 LPC_SERIRQ B50 CB_RESET C50 DDI3_PAIR3 D50 DDI2_PAIR3 A51 GND FIXED B51 GND FIXED C51 GND FIXED D51 GND FIXED A52 PCIE_TX5 B52 PCIE_RX5 C52 PEG_RX0 D52 PEG_TX0 A53 PCIE_TX5 B53 PCIE_RX5 C53 PEG_RX0 D53 PEG_TX0 A54 GPI0 B54 GPO1 C54 TYPE0 D54 PEG_LANE_RV A55 PCIE_TX4 B55 PCIE_RX4 C55 PEG_RX1 D55 PEG_TX1 A56 PCIE_TX4 B56 PCIE_RX4 C56...

Page 47: ...GND FIXED B70 GND FIXED C70 GND FIXED D70 GND FIXED A71 LVDS_A0 B71 LVDS_B0 C71 PEG_RX6 D71 PEG_TX6 A72 LVDS_A0 B72 LVDS_B0 C72 PEG_RX6 D72 PEG_TX6 A73 LVDS_A1 B73 LVDS_B1 C73 GND D73 GND A74 LVDS_A1 B74 LVDS_B1 C74 PEG_RX7 D74 PEG_TX7 A75 LVDS_A2 B75 LVDS_B2 C75 PEG_RX7 D75 PEG_TX7 A76 LVDS_A2 B76 LVDS_B2 C76 GND D76 GND A77 LVDS_VDD_EN B77 LVDS_B3 C77 RSVD D77 RSVD A78 LVDS_A3 B78 LVDS_B3 C78 PE...

Page 48: ...D FIXED D90 GND FIXED A91 SPI_POWER B91 VGA_GRN C91 PEG_RX12 D91 PEG_TX12 A92 SPI_MISO B92 VGA_BLU C92 PEG_RX12 D92 PEG_TX12 A93 GPO0 B93 VGA_HSYNC C93 GND D93 GND A94 SPI_CLK B94 VGA_VSYNC C94 PEG_RX13 D94 PEG_TX13 A95 SPI_MOSI B95 VGA_I2C_CK C95 PEG_RX13 D95 PEG_TX13 A96 TPM_PP B96 VGA_I2C_DAT C96 GND D96 GND A97 TYPE10 B97 SPI_CS C97 RSVD D97 RSVD A98 SER0_TX B98 RSVD C98 PEG_RX14 D98 PEG_TX14 ...

Page 49: ...VCC_12V C105 VCC_12V D105 VCC_12V A106 VCC_12V B106 VCC_12V C106 VCC_12V D106 VCC_12V A107 VCC_12V B107 VCC_12V C107 VCC_12V D107 VCC_12V A108 VCC_12V B108 VCC_12V C108 VCC_12V D108 VCC_12V A109 VCC_12V B109 VCC_12V C109 VCC_12V D109 VCC_12V A110 GND FIXED B110 GND FIXED C110 GND FIXED D110 GND FIXED not supported on MSC C6B SLH modules ...

Page 50: ...horting the pins of this jumper during boot the system is forced into crisis recovery mode For more information see chapter 6 18 RTC Reset By shorting the pins of this jumper the RTC Clock is reset and the values of the CMOS NV RAM are cleared This jumper is only functional in systems with battery at RTC power supply The main power must be switched off before shorting the jumper These jumpers are ...

Page 51: ...put for the tacho signal from the fan open collector two pulses rotation 4 PWM PWM output signal for fan speed control 4 Watchdog The C6B SLH board has a watchdog function implemented by an embedded controller The watchdog can be enabled and configured in the BIOS Setup If the watchdog is enabled a counter is started which generates a reset if it is not retriggered within a programmable time windo...

Page 52: ... ME 22 0 3 0 A B C D SATA Controller 23 0 0 x LPSS UART Controller 0 30 0 0 x LPSS UART Controller 1 30 1 0 x LPSS SPI Controller 0 unused 30 2 0 x LPSS SPI Controller 1 unused 30 3 0 x LPC Bridge 31 0 0 A B C D High Definition Audio 31 3 0 x SMBus 31 4 0 x GbE 31 6 0 x Trace Hub 31 7 0 x PCIe Slot 1 Lane 0 1D 0 dyn A B C D PCIe Slot 2 Lane 1 1D 1 dyn D A B C PCIe Slot 3 Lane 2 1D 2 dyn C D A B PC...

Page 53: ...are not shared with chipset devices NOTE The assignment of the Chipset Pcie Lanes to the Com Express Lane can be seen in Bios Menu PCIe Express Configuration NOTE PCIe Port 4 is assigned to internal LAN device 5 2 SMB Address Map Device Address SO DIMM 0 SPD EEPROM A0h 50h SO DIMM 1 SPD EEPROM A4h 52h CMOS Backup EEPROM A8h 54h AAh 55h Embedded Controller C0h 60h ANX1122 50h 28h ANX1122 8Ch 46h 8 ...

Page 54: ...p The standard boot screen is a black screen without any logo 6 3 Activity Detection Background While the startup screen is displayed press the Setup Entry key ESC or DEL The system acknowledges the input and at the end of POST the screen clears and setup launches 6 4 Aptio Setup Utility With the AMI Aptio Setup program you can modify Aptio settings and control the special features of your compute...

Page 55: ...itoring Power Performance PCH IO Configuration User Password System Information PCH FW Configuration Flat Panel Configuration HDD Password Firmware Update Thermal Configuration Secure Boot Intel ICC Intel Rapid Storage Technology Trusted Computing ACPI Settings SMART Settings Serial Port Console Redirection Intel TXT Information AMI Graphical Output Network Stack Configuration CSM Configuration NV...

Page 56: ... set the Advanced Features available on your system s chipset Chipset Use this menu to set Chipset Features Security Use this menu to set User and Supervisor Passwords and the Backup and Virus Check reminders Boot Use this menu to set the boot order in which the BIOS attempts to boot to OS Save Exit Saves and Exits the Aptio setup utility Use the left and right arrow keys on your keyboard to make ...

Page 57: ...Item Change Option F1 General Help window F2 Previous Values F3 Optimized Defaults F4 Save and Exit Select an item To select an item use the arrow keys to move the cursor to the field you want Then use the plus and minus value keys to select a value for that field Alternatively the Enter key can be used to select a value from a Pop Up menu The Save Values commands in the Exit Menu save the values ...

Page 58: ...hows the Project Version Build Date Informative Shows the Build Date Access Level Informative This feature shows what kind of user has entered the Aptio setup It depends on the Security Tab if a Administrator and or User password is set MSC Board Info Submenu Shows board specific information Hardware Monitoring Measurement Submenu Shows the hardware sensors monitoring System Information Submenu Sh...

Page 59: ...mperature of the System ever measured System Max Temperature Informative Shows the highest temperature of the System ever measured Memory Min Temperature Informative Shows the lowest temperature of the Memory ever measured Memory Max Temperature Informative Shows the highest temperature of the Memory ever measured Board Min Temperature Informative Shows the lowest temperature of the board ever mea...

Page 60: ...does not reflect CPU die temperature System Temperature Informative Shows CPU Temperature Memory Temperature Informative Shows Memory Temperature Board Temperature Informative Shows Board Temperature VCore Informative Shows the VCore voltage 3 3V Informative Shows the 3 3V voltage 5V Informative Shows the 5V voltage 5V Standby Informative Shows the current 5V Standby voltage 12V Informative Shows ...

Page 61: ...y Entire Flash BIOS only Entire Flash Update Entire Flash Preserve SMBIOS Variable Enabled Disabled If Enabled restore SMBIOS Variables DMI Table after Firmware Update In particular the board s UUID is preserved Preserve Boot Option Priorities Enabled Disabled If Enabled restore Boot Option Priorities after Firmware Update This option does not restore the Advanced Boot Device Selection in Boot Men...

Page 62: ...SMART Settings Serial Port Console Redirection Submenu Serial Port Console Redirection Intel TXT Information Submenu Intel TXT Information Network Stack Configuration Submenu Network Stack Configuration CSM Configuration Submenu CSM Configuration NVMe Configuration Submenu NVMe Configuration SDIO Configuration Submenu SDIO Configuration USB Configuration Submenu USB Configuration SIO WB627 Configu...

Page 63: ...CPU dependent This value must be between Max Efficiency Ratio LFM and Maximum non turbo ratio set by Hardware HFM Hardware Prefetcher Enabled Disabled To turn on off the MLC streamer prefetcher Adjacent Cache Line Prefetch Enabled Disabled To turn on off prefetching of adjacent cache lines Intel VMX Virtualization Technology Enabled Disabled When enabled a VMM can utilize the additional hardware c...

Page 64: ...re CPU SMM Enhancement Submenu CPU SMM Enhancement Submenu FCLK Frequency for Early Power On Normal 800MHz 1 Ghz 400 Mhz FCLK frequency can take values of 400MHz 800MHz and 1GHz 1GHz not supported for ULT ULX SKUs Only relevant for PEG Port NOTE Without CMOS battery system will perform an extra powercycle If it should not happen set to 800 Mhz Performance on PEG is less than3 lower if set to 800MH...

Page 65: ...gement Control Feature Options Description Boot performance mode Max non Turbo Performance Max Battery Turbo Performance Select the performance state that the BIOS will set starting from reset vector Intel R SpeedStep tm Enabled Disabled Allows more than two frequency ranges to be supported Race To Halt RTH Enabled Disabled Race To Halt RTH Intel R Speed Shift Technology Enabled Disabled Enable Di...

Page 66: ... Demotion C1 C3 C1 and C3 Disabled Configure C State Auto Demotion C State Un demotion C1 C3 C1 and C3 Disabled Configure C State Un demotion Package C State Demotion Enabled Disabled Auto Enable or Disable Package C State Demotion 0 Disable 1 Enable b 2 Auto b Auto Enabled for Skylake Disabled for Kabylake Package C State Un demotion Enabled Disabled Auto Enable or Disable Package C State UnDemot...

Page 67: ...abled Disabled Enable disable Energy Performance Gain 6 8 5 View Configure Turbo Options Feature Options Description Energy Efficient P state Enabled Disabled Enable Disable Energy Efficient P state feature When set to 0 will disable access to ENERGY_PERFORMANCE_BIAS MSR and CPUID Function 6 ECX 3 will read 0 indicating no support for Energy Efficient policy setting When set to 1 will enable acces...

Page 68: ...for Power Limit 2 Power Limit 2 Value Power Limit 2 value in Milli Watts BIOS will round to the nearest 1 8W when programming If the value is 0 BIOS will program this value as 1 25 TDP For 12 50W enter 12500 Processor applies control policies such that the package power does not exceed this limit 1 Core Ratio Limit Override 0 83 1 Core Ratio Limit with range 0 to 83 The Minimum range may vary betw...

Page 69: ...Min Power Limits specified by PACKAGE_POWER_SKU_MSR Other SKUs This value must be between Min Power Limit and TDP Limit Power Limit 2 Value Power Limit 2 value in Milli Watts BIOS will round to the nearest 1 8W when programming 0 no custom override For 12 50W enter 12500 Processor applies control policies such that the package power does not exceed this limit Power Limit 1 Time Window Value Power ...

Page 70: ...mit 1 Value Power Limit 1 in Milli Watts BIOS will round to the nearest 1 8W when programming 0 no custom override For 12 50W enter 12500 Overclocking SKU Value must be between Max and Min Power Limits specified by PACKAGE_POWER_SKU_MSR Other SKUs This value must be between Min Power Limit and TDP Limit Power Limit 2 Value Milli Watts BIOS will round to the nearest 1 8W when programming 0 no custo...

Page 71: ...ound to the nearest 1 8W when programming For 12 50W enter 12500 XE SKU Any value can be programmed Overclocking SKU Value must be between Max and Min Power Limits specified by PACKAGE_POWER_SKU_MSR Other SKUs This value must be between Min Power Limit and TDP Limit If the value is 0 BIOS leaves default value Power Limit 3 Time Window Value Power Limit 3 Time Window value in Milli seconds The valu...

Page 72: ...00 Mhz x Select max GT frequency 6 8 11 PCH FW Configuration Feature Options Description ME State Enabled Disabled When Disabled ME will be put into ME Temporarily Disabled Mode Manageability Feature Enabled Disabled Enable Disable Intel Manageabiltity features AMT BIOS Features Enabled Disabled When disabled AMT BIOS features are no longer supported and user is no longer able to access MEBx Setup...

Page 73: ... Enabled Disabled Enable Disable Alert Standard Format support USB Provisioning of AMT Enabled Disabled Enable Disable of AMT USB Provisioning CIRA Configuration Submenu CIRA Configuration ASF Configuration Submenu ASF Configuration Secure Erase Configuration Submenu Secure Erase Configuration OEM Flags Settings Submenu OEM Flags Settings MEBx Resolution Settings Submenu MEBx Resolution Settings 6...

Page 74: ...ription PET Progress Enabled Disabled Enable Disable PET Events Progress to receive PET Events WatchDog Enabled Disabled Enable Disable WatchDog Timer OS Timer Value Set OS watchdog timer BIOS Timer Value Set BIOS watchdog timer 6 8 15 Secure Erase Configuration Feature Options Description Secure Erase mode Enabled Disabled Change Secure Erase module behavior Simulated Performs SE flow without era...

Page 75: ...enter ME Configuration Screens Press 2 to initiate a remote connection NOTE Network Access must be activated from MEBx Setup for this screen to be displayed Hide Unconfigure ME Confirmation Prompt Enabled Disabled OEMFlag Bit 6 Hide Unconfigure ME confirmation prompt when attempting ME unconfiguration MEBx OEM Debug Menu Enable Enabled Disabled OEMFlag Bit 14 Enable OEM debug menu in MEBx Unconfig...

Page 76: ...nfiguration Feature Options Description Me FW Image Re Flash Enabled Disabled Enable Disable Me FW Image Re Flash function 6 8 19 Thermal Configuration Feature Options Description CPU Thermal Configuration Enabled Disabled Turn TPM Enable Disable NOTE Your Computer will reboot during restart in order to change State of TPM Platform Thermal Configuration None Enable take ownership Disable take owne...

Page 77: ... offset time window can range from 5ms to 448s For SKL Y SKU the recommended default is 5 Sec and all other SKUs the recommended default are disabled Tcc Offset Clamp Enable Enabled Disabled Tcc Offset Clamp bit Enable for Running Average Temperature Limit RATL feature to allow CPU to throttle below P1 Tcc Offset Lock Enable Enabled Disabled Lock Enable for Running Average Temperature Limit RATL f...

Page 78: ...esolve rare PECI related C10 issues Via pcode mailbox command 0x24 Default is disabled no command sent 6 8 21 Platform Thermal Configuration Feature Options Description Critical Trip Points Enabled Disabled Disable Critical Trip Points PCH Thermal Device Enabled in PCI Mode Enabled in ACPI Mode Disabled Enable Disable PCH Thermal Device D20 F2 6 8 22 Intel ICC Feature Options Description ICC OC Wa...

Page 79: ...m capabilites Tpically profile 0 has failsafe settings Other profiles correspond to WiMax 3G or Overclocking settings 6 8 23 Intel Rapid Storage Technology Feature Options Description Create Raid Volume Enter Enter Raid configuration menu to build a Raid0 RAID1 RAID5 RAID 10 SATA Disks Informative Shows information about initilasied SATA Disks 6 8 24 Trusted Computing Feature Options Description T...

Page 80: ...highest ACPI sleep state the system will enter when the SUSPEND button is pressed Lock Legacy Resources Enabled Disabled Enables or Disables Lock of Legacy Resources 6 8 26 Smart Settings Feature Options Description SMART Self Test Enabled Disabled Run SMART Self Test on all HDDs during POST 6 8 27 Serial Port Console Redirection Feature Options Description Com 0 6 Console Redirection Enabled Disa...

Page 81: ...ons Description Terminal Type ANSI VT100 VT100 VT UTF8 Emulation ANSI Extended ASCII char set VT100 ASCII char set VT100 Extends VT100 to support color function keys etc VT UTF8 Uses UTF8 encoding to map Unicode chars onto 1 or more bytes Bits per second 9600 19200 38400 57600 115200 Selects serial port transmission speed The speed must be matched on the other side Long or noisy lines may require ...

Page 82: ...is to capture Terminal data Resolution 100x31 Disabled Enabled Enables or disables extended terminal resolution Legacy OS Redirection 80x24 80x25 On Legacy OS the number of rows and Columns supported redirection Putty KeyPad VT100 Linux XTERMR6 SCO ESCN VT400 Select FunctionKey and KeyPad on Putty Redirection after BIOS POST Always Enable Bootloader The Settings specify if BootLoader is selected t...

Page 83: ...arts or stops the BIST on the integrated display panel 6 8 31 Network Stack Configuration Feature Options Description Network Stack Enabled Disabled Enable Disable UEFI Network Stack Ipv4 PXE Support Enabled Disabled Enable Disable IPv4 PXE boot support If disabled IPv4 PXE boot support will not be available Ipv4 HTTP Support Enabled Disabled Enable Disable IPv4 HTTP boot support If disabled IPv4 ...

Page 84: ...Set display mode for Option ROM INT19 Trap Response Immediate Postponed BIOS reaction on INT19 trapping by Option ROM IMMEDIATE execute the trap right away POSTPONED execute the trap during legacy boot Boot option filter Legacy only UEFI only Legacy and UEFI This option controls Legacy UEFI ROMs priority Network Do not launch Legacy UEFI Controls the execution of UEFI and Legacy PXE OPROM NOTE for...

Page 85: ...de 6 8 35 USB Configuration Feature Options Description Legacy USB Support Auto Enabled Disabled Enables Legacy USB support AUTO option disables legacy support if no USB devices are connected DISABLE option will keep USB devices available only for EFI applications USB 2 0 Controller Mode HiSpeed FullSpeed Configures the USB 2 0 controller in HiSpeed 480Mbps or FullSpeed 12Mbps XHCI Legacy Support ...

Page 86: ...Interrupt transfers Device reset time out 10 20 30 40 sec USB mass storage device Start Unit command time out Device power up delay Auto Manual Maximum time the device will take before it properly reports itself to the Host Controller Auto uses default value for a Root port it is 100 ms for a Hub port the delay is taken from Hub descriptor Device power up delay Value 1 40 Delay range is 1 40 secon...

Page 87: ...IRQ 3 4 5 6 7 10 11 12 Resource setting for COM A D on Winbond SIO LPT Disabled Enabled Enable or disable LPT on Winbond SIO LPT Setting Auto I O 378h IRQ 5 7 I O 278 IRQ 5 7 Resource setting for LPT A on Winbond SIO LPT Mode SPP EPP 1 9 ECP ECP EPP 1 9 Printer Mode EPP 1 7 ECP EPP 1 7 Mode setting for LPT on Winbond SIO PS 2 controller Enabled Disabled Enable or disable the PS 2 controller HWM In...

Page 88: ... System Fan Control Manual Temperature based Define how the fan should be controlled manually set to a fixed duty cycle or temperature based auto control Fan Speed Off 25 50 75 100 Setup the fan duty cycle for manual fan control By CPU sensor Enabled Disabled If enabled the cpu fan will be controlled by this temperature sensor By System sensor Enabled Disabled If enabled the cpu fan will be contro...

Page 89: ... degrees Celsius at which the fan should be set to maximum speed duty cycle NOTE This option depends on selected temperature source CPU System Board or a combination of these CPU System Memory Board Temperature Limit T3 C 60 C 70 C 80 C 90 C 100 C Temperature threshold in degrees Celsius at which the fan should be set to maximum speed duty cycle NOTE This option depends on selected temperature sou...

Page 90: ...ne of the external temperature sensors and is set to manual mode per default In temperature based mode up to three different sources can be selected CPU temperature board temperature sensor and system temperature sensor Temperature based mode controls fan within 4 temperature zones and fixed PWM duty cycles PWMmin 25 PWMmid 50 PWMmax 100 The temperature zones can be selected by temperature limits ...

Page 91: ...limit for maximum Fan speed selectable by SETUP Thyst Temperature hysteresis selectable by SETUP Temperature Control with multiple Sensors Fan control allows the association of any temperature sensor supported by embedded controller This allows active fan control for more than one temperature The supported temperature sensors are associated with the following onboard temperature areas CPU temperat...

Page 92: ...ComExpress SER0 or SER1 signals To be able to disable HS UART Port0 the SDCard Controller and HS UART Port1 must also be disabled GPIO Controller Enabled Disabled Enables Disables the GPIO Controller Watchdog Start on Boot No Yes Start the watchdog after bios POST if enabled Startup Delay 1s 10s 30s 1min 5min Select the initial delay value This is an additional one time delay before the standard t...

Page 93: ...p Enabled Disabled Intel ME Crypto Transport Layer Security TLS Disable no confidentiality Enable with confidentiality External SMBus Control Enabled Disabled Enable Disable External SMBus after POST 6 8 39 Onboard GPIO Initialization Warning It is important to ensure that on carrier board side the GPIOs can not cause shorts in case of switching the GPIOs direction In worst case this can damage th...

Page 94: ...generated GPIO 5 Capabilities Input Output EAPI GPIO 5 Capabilitie is input or output GPIO 5 Default Value Output High Output Low Define the default value for this GPIO Interrupt Capabilities Both Edges Rising Edge Falling Edge Define the condition under which an interrupt is generated GPIO 6 Capabilities Input Output EAPI GPIO 6 Capabilitie is input or output GPIO 6 Default Value Output High Outp...

Page 95: ...ual Automatic Manual stop grant configuration Number of Stop Grant Cycles Value Selects number of Stop Grant cycles VT d Enabled Disabled VT d capability CHAP Device B0 D7 F0 Enabled Disabled Enable Disable Challenge Handshake Authentication Protocol Device Thermal Device B0 D4 F0 Enabled Disabled Enable Disable SA Thermal Device GMM Device B0 D8 F0 Enabled Disabled Enable Disable Gaussian Mixture...

Page 96: ...intel recommendation for 64bit OS s but does not work for 32bit OS s By selecting 3 5GB the BIOS will automatically reduce the TOLUD value to the optimum value according to the PCIe space required You should then see in Windows what memory is available SA GV Enabled Disabled Fixed Low Fixed High System Agent Geyserville Fixed Low High SA GV disabled MRC only runs tasks from Low or High point SA GV...

Page 97: ... Disabled Enable Disable VC1 Read Metering Feature RdMeter VC1 RdMeter Time Window Value VC1 Read Metering Time Window time window over which VC1 read request counter is tracked Configurable for tens of microseconds window size VC1 RdMeter Threshold Value VC1 Read Metering Threshold threshold of counter within time window Strong Weak Leaker Value Value for StrongWkLeaker Memory Scrambler Enabled D...

Page 98: ...f External Gfx Card Enabled Disabled If Enable it will not scan for External Gfx Card on PEG and PCH PCIE Ports Primary Display Auto IGFX PCIE Select which of IGFX PEG PCI Graphics device should be Primary Display Or select SG for Switchable Gfx Internal Graphics Auto Enabled Disabled Keep IGFX enabled based on the setup options GTT Size 2 MB 4MB 8MB Select the GTT Size Aperture Size 128MB 4096MB ...

Page 99: ...PCIe Bifurcation allows configurations B0 D1 x16 F0 x8 F0 x8 F1 x8 F0 X4 F1 x4 F2 Enable Root Port Auto Enabled Disabled Enable or Disable the Root Port Max Link Speed Auto Gen1 Gen3 Configure PEG 0 1 0 Max Speed Max Link Width Auto Force x1 Force X2 Force X4 Force X8 Force PEG link to retrain to X1 2 4 8 Power Down Unused Lanes Auto Disabled Power Down Unused Lanes Disabled No power saving Auto B...

Page 100: ...Auto Default Device Capability or force to 128 256 Bytes Detect Non Compliance Device Enabled Disabled Detect Non Compliance PCI Express Device in PEG Program PCIe ASPM after OpROM Enabled Disabled Enabled PCIe ASPM will be programmed after OpROM Disabled PCIe ASPM will be programmed before OpROM Program Static Phase1 Eq Enabled Disabled Program Phase1 Presets CTLEp Always Attempt SW EQ Enabled Di...

Page 101: ... will Suppress I2C Sensor Hub Setup Option I2C Will Suppress ALS Setup Option and USB will Suppress Both I2C and ALS Wake on LAN Enabled Disabled Enable or disable integrated LAN to wake the system The Wake On LAN cannot be disabled if ME is on at Sx state K1 off Enabled Disabled Enable or disable K1 off feature CLKREQ Disable DSX ACPRESENT PullDown Enabled Disabled Disable PCH internal ACPRESENT ...

Page 102: ...led Disabled Enables Disables IOAPIC 24 119 Entries IRQ24 119 may be used by PCH devices Disabling those interrupts may cause certain devices failure Unlock PCH P2SB Enabled Disabled Unlock PCH P2SB SBI and Configuration space by PSF PMC READ DISABLE Enabled Disabled This is TEST feature for PMC XRAM read Flash Protection Range Registers FPRR Enabled Disabled Enable Flash Protection Range Register...

Page 103: ... Enable Disable Peer Memory Write Enable Enabled Disabled Peer Memory Write Enable Disable Compliance Test Mode Enabled Disabled Enable when using Compliance Load Board PCIe USB Glitch W A Enabled Disabled PCIe USB Glitch W A for bad USB device s connected behind PCIE PEG Port PCIe function swap Enabled Disabled When Disabled prevents PCIE rootport function swap If any function other than 0th is e...

Page 104: ...ane 2 Submenu Submenu PCIe Root Port 12 COMExpress lane 3 Submenu Submenu 6 9 7 PCIE GEN3 Eq Parameters Feature Options Description PCIex Cm Value PCIex Cm PCIe Cp Value PCIe CP Override SW EQ settings Enabled Disabled Override SW EQ settings 6 9 8 PCIe Root Port x Feature Options Description PCI Express Root Port Enabled Disabled Control the PCI Express Root Port ASPM Support Disabled L0s L1 L0sL...

Page 105: ...I Express Completion Timer TO SEFE Enabled Disabled Enable or disable Root PCI Express System Error on Fatal Error SENFE Enabled Disabled Enable or disable Root PCI Express System Error on Non Fatal Error SECE Enabled Disabled Enable or disable Root PCI Express System Error on Correctable Error PME SCI Enabled Disabled Enable or disable PCI Express PME SCI Hot Plug Enabled Disabled Enable or disab...

Page 106: ...Enable LTR override values will be forced and LTR messages from the device will be ignored 6 9 9 SATA Intel RST RAID Configuration NOTE Raidsetup can be configured under Setup Menu Advanced in Intel Rapid Storage Technology Submenu Feature Options Description SATA Controller s Enable Disable SATA Device SATA Mode Selection AHCI Intel RST Premium Determines how SATA controllers operate Note To enab...

Page 107: ...e performed and only the drives which have this option enabled will spin up at boot Otherwise all drives spin up at boot SATA Device Type for Port x Enabled Disabled Identify the SATA port is connected to Solid State Drive or Hard Disk Drive NOTE Using Intel Optane Memory for Acceleration only possible on KLH Make sure to use the x4 Bios Image so PCIe Port is configured as x4 Select Sata Mode Sele...

Page 108: ...al IRRT Only on eSATA Enabled Disabled If enabled then only IRRT volumes can span internal and eSATA drives If disabled then any RAID volume can span internal and eSATA drives Smart Response Technology Enabled Disabled Enable or Disable Smart Response Technology NOTE Intel Smart Response Technology is a feature of Intel Rapid Storage Technology Intel RST that enables either a dual drive lower cost...

Page 109: ...ect the USB port functionality on physical connector To disable USB port completely disable USB3 0 as well as USB2 0 functionality USB 2 0 on Connector 0 7 Enabled Disabled Select the USB port functionality on physical connector To disable USB port completely disable USB3 0 as well as USB2 0 functionality 6 9 12 Security Feature Options Description RTC Lock Enabled Disabled Enable will lock bytes ...

Page 110: ...ability of Audio Controller 6 9 14 Flat Panel Configuration Feature Options Description Flat Panel Interface Enabled Disabled Select LFP Interface either eDP or LVDS which depends upon HW option LVDS Panel Type 640x480 800x600 1024 768 1280x1024 1 1600x1200 1366x768 1680x1050 1920x1200 1440x900 1600x900 1280x800 1920x1080 Selected panel type is used if valid EDID data cannot be found in external E...

Page 111: ...ct the Video Device which will be activated during POST This has no effect if external graphics present Secondary boot display selection will appear based on your selection VGA modes will be supported only on primary display Panel Scaling Auto Off Force Scaling Select the LCD panel scaling option used by the Internal Graphics Device Backlight Control PWM normal PWM inverted Back Light Control Sett...

Page 112: ...Table 6 1 BIOS Security Menu Feature Options Description Administrator Password Set Password Set Setup Administrator Password User Password Set Password Set User Password HDDSecurity Configuration Set Password Set HDD Password Secure Boot Submenu Secure Boot Configurations NOTE If ONLY the Administrator s password is set then this only limits access to Setup and is only prompted for when entering ...

Page 113: ...ard Custom In Custom mode Secure Boot Variables can be configured without authentication Key Management Submenu Enables expert users to modify Secure Boot Policy variables without full authentication 6 10 2 Key Management Feature Options Description Provision Factory Defaults Enabled Disabled Allow to provision factory default Secure Boot keys when System is in Setup Mode Reset to Setup Mode Enter...

Page 114: ...ed Signatures Enter Forbidden Signatures Enter Authorized TimeStamps Enter OsRecovery Signatures Enter 6 11 Boot Table 6 2 BIOS Boot Menu Feature Options Description Setup Prompt Timeout 1 65535sec Number of seconds to wait for setup activation key 65535 0xFFFF means wait forever Bootup NumLock State On Off Select the keyboard NumLock state Quiet Boot Enabled Disabled Enables Disables Quiet Boot o...

Page 115: ...k driver will be skipped Boot Priority 1 None SATA Ports Internal SATA 0 SATA 1 SATA 2 SATA 3 SATA RAID Internal USB Ports Internal USB Ports 0 1 2 Legacy LAN UEFI LAN Internal External Devices Define which boot device should have the highest boot priority NOTE If the connected device has a legacy and uefi boot path uefi will be the higher priority This can be avoided by filtering UEFI Boot out Bo...

Page 116: ...ice will be bootable If set to UEFI only UEFI devices will be bootable Boot Option 1 Device x Sets the system boot order Please note that UEFI boot entries will always have the highest priority This list will be updated during next boot depending on the settings in the Advanced Boot Device Selection Note The number of available Boot options is dependent on the devices which are connected This wind...

Page 117: ...ot to fail reboot and press ESC or DEL to enter Setup In Setup you can restore the Default Values as described below or try to change the selections that caused the boot to fail Discard Changes and Exit Exit system setup without saving any changes Save Changes and Reset When you have completed the system configuration changes select this option to save the changes and reboot the system so the new ...

Page 118: ...lect any of the options to select to the particular device and boot directly from it Launch EFI Shell from filesystem device Attempts to Launch EFI Shell application Shellx64 efi from one of the available filesystem devices WARNING This function will still work even if mass storage devices are not registered into the boot device list via MSC BIOS Configuration tool MBconf tool For example only Har...

Page 119: ...Image location within file system Recovery FlashImg bin To start the update make sure that the medium with the correct BIOS stored is connected and Update Source is set to Local Block Devices In Bios section Main MSC Firmware Update configure control flags as needed Then enter Start firmware Update After Bios update is done system will reboot NOTICE Do not reset or power cycle the board during upd...

Page 120: ...arameters Here is an example of a simple txt file which contains the network configuration data it is loaded by Autflash with the switches net nc Filename e g AutoFlash efi u e net fc configfile txt Network Interface 0 Config Mode DHCP Network Protocol TFTP Server Address Mode static Server Name testserver testnet com File Name Mode manual Image File Name Boot Bios FlashImg bin ...

Page 121: ...instructions on screen 7 Do NOT switch off power and wait until BIOS update has completed 6 15 Bios Update from Linux It is also possible to trigger the update from Linux Make sure the Image location is within file system Recovery FlashImg bin and the device is inserted as described in 6 13 To start the update from Linux run the AutoFLASH tool as root and probably set the permission for the file w...

Page 122: ...t can happen that the system will not boot In this case it is possible to restore the Bios with the following method 1 Prepare the SPI Image flashimg bin as described in section 6 13 2 Power on the system 3 Bios will search for the file and if found a Bios recovery will be started 4 After Bios recovery is finished the system will perform a powercycle and the system should boot normal again without...

Page 123: ...owing functions are provided customization of default BIOS setup parameters Hiding or removing access to setup nodes newer APTIO 5 based AMI BIOS only addition of custom boot logo splashscreen custom LCD panel timing EDID Boot priority selection importing trusted keys For more details please refer to the Application note on the MSC website ...

Page 124: ...tect its own flash to prevent malicious applications from changing the bios code This write protection can only be disabled by a global reset so flash writes can only be done by the bios code itself Hash based checksum checks for bios images Bios images include a hash based checksum to safeguard against file and or memory corruption This hash will be checked before programming a new bios Bios upda...

Page 125: ...port in a variety of ways With a live system go into setup and enter the Firmware Update submenu If the last line starts with Trusted Update it is supported in this bios version When you load a bios image into the MSC bios editor V2 30 or later bios images with support for Trusted Update will show a tab called Trusted Update Ask your MSC contact if the bios for your platform supports this feature ...

Page 126: ...y crt OpenSSL generates keys in a different format therefore some conversion must be done before those keys can be used for Trusted Update However all required conversion can be done with the openssl tool as seen above The important files are the private key file key pfx and the public key certificate key cer Trusted Update key usage MakeCert or OpenSSL will prompt you for a password when generati...

Page 127: ... private key pfx file and enter the required password into the boxes below 5 Now save your bios image and the bios file will be updated with the provided public key and a signature for Trusted Update will be generated and added to the bios image Example Usage Switching from unsigned to signed updates If your currently running bios has Trusted Update not enable yet you only need to set a public key...

Page 128: ... pins of this jumper during boot the system is forced into crisis recovery mode RTC Reset By shorting the pins of this jumper the RTC Clock is reset and the values of the CMOS NV RAM are cleared SRTC Reset By shorting the pins of this jumper the manageability register bits in the CMOS NV RAM are reset For more information see chapter 3 1 6 22 Post Codes For Post Code information please look on the...

Page 129: ...ives where the data between the two is mirrored in real time Because all of the data is duplicated the operating system treats the usable space of a RAID 1 array as the maximum size of one hard drive in the array For example two 120GB hard drives in a RAID 1 array will appear as a single 120GB hard drive to the operating system A RAID 5 array is three or more hard drives with data divided into man...

Page 130: ... technology that enables the processor to run above its base operating frequency via dynamic control of the CPU s clock rate It is activated when the operating system requests the highest performance state of the processor The increased clock rate is limited by the processor s power current and thermal limits as well as the number of cores currently in use and the maximum frequency of the active c...

Page 131: ...bility security and flexibility in IT environments virtualization technologies like hardware assisted Intel Virtualization Technology Intel VT combined with software based virtualization solutions provide maximum system utilization by consolidating multiple environments into a single server or PC By abstracting the software away from the underlying hardware a world of new usage models opens up tha...

Page 132: ... hash key summary of the hardware and software configuration The program encrypting the data determines the extent of the summary of the software This allows a third party to verify that the software has not been changed Binding encrypts data using the TPM endorsement key a unique RSA key burned into the chip during its production or another trusted key descended from it Sealing encrypts data in s...

Page 133: ...og timer view sensor values of hardware monitor MSC provides a software package which is downloadable here after registration www msc technologies eu de support boards 9 MSC Password Configuration Tool MSC provides a tool for writing or change the Bios password under EFI shell Win10 or Linux The OS must be installed in UEFI mode To obtain the tool please contact the Avnet Integrated MSC Technical ...

Page 134: ...tallation If Windows Installation setup does not allow to install on harddisk try to make harddisk the first boot device in Bios setup Issue 4 No USB available during Windows 7 Setup In spite of being available in BIOS setup no USB is available during Windows 7 Setup from any standard install media This is because the C6B SLH has no EHCI controller anymore but just XHCI and Windows 7 does not have...

Page 135: ...MSC C6B SLH MSC C6B SLH User Manual 135 144 For additional help please contact Avnet Integrated MSC Technical Support Phone 49 8165 906 200 Email support boards avnet eu ...

Page 136: ...ct openssl core openssl org OpenSSL License Copyright c 1998 2011 The OpenSSL Project All rights reserved Redistribution and use in source and binary forms with or without modification are permitted provided that the following conditions are met 1 Redistributions of source code must retain the above copyright notice this list of conditions and the following disclaimer 2 Redistributions in binary f...

Page 137: ...from this software may not be called OpenSSL nor may OpenSSL appear in their names without prior written permission of the OpenSSL Project 6 Redistributions of any form whatsoever must retain the following acknowledgment This product includes software developed by the OpenSSL Project for use in the OpenSSL Toolkit http www openssl org THIS SOFTWARE IS PROVIDED BY THE OpenSSL PROJECT AS IS AND ANY ...

Page 138: ...POSSIBILITY OF SUCH DAMAGE This product includes cryptographic software written by Eric Young eay cryptsoft com This product includes software written by Tim Hudson tjh cryptsoft com Original SSLeay License Copyright C 1995 1998 Eric Young eay cryptsoft com All rights reserved This package is an SSL implementation written by Eric Young eay cryptsoft com The implementation was written so as to conf...

Page 139: ...or textual provided with the package Redistribution and use in source and binary forms with or without modification are permitted provided that the following conditions are met 1 Redistributions of source code must retain the copyright notice this list of conditions and the following disclaimer 2 Redistributions in binary form must reproduce the above copyright notice this list of conditions and t...

Page 140: ...TRIBUTORS BE LIABLE FOR ANY DIRECT INDIRECT INCIDENTAL SPECIAL EXEMPLARY OR CONSEQUENTIAL DAMAGES INCLUDING BUT NOT LIMITED TO PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES LOSS OF USE DATA OR PROFITS OR BUSINESS INTERRUPTION HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY WHETHER IN CONTRACT STRICT LIABILITY OR TORT INCLUDING NEGLIGENCE OR OTHERWISE ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE ...

Page 141: ...ons are met 1 Redistributions of source code must retain the above copyright notice this list of conditions and the following disclaimer 2 Redistributions in binary form must reproduce the above copyright notice this list of conditions and the following disclaimer in the documentation and or other materials provided with the distribution 3 Neither the name s of the above listed copyright holder s ...

Page 142: ...AL EXEMPLARY OR CONSEQUENTIAL DAMAGES INCLUDING BUT NOT LIMITED TO PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES LOSS OF USE DATA OR PROFITS OR BUSINESS INTERRUPTION HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY WHETHER IN CONTRACT STRICT LIABILITY OR TORT INCLUDING NEGLIGENCE OR OTHERWISE ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE Features I...

Page 143: ...goal is to add full WPA WPA2 support to Linux wireless extensions to allow new drivers to be supported without having to implement new driver specific interface code in wpa_supplicant WPA The original security mechanism of IEEE 802 11 standard was not designed to be strong and has proven to be insufficient for most networks that require some kind of security Task group I Security of IEEE 802 11 wo...

Page 144: ...A at its web site http www wi fi org OpenSection protected_access asp IEEE 802 11 standard defined wired equivalent privacy WEP algorithm for protecting wireless networks WEP uses RC4 with 40 bit keys 24 bit initialization vector IV and CRC32 to protect against packet forgery All these choices have proven to be insufficient key space is too small against current attacks RC4 key scheduling is insuf...

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