Topology
A block diagram of the circuitry is shown below:
FPGA
Partial-
Field
Memory
Video
ADC
and
De coder
V i d e o
DAC,
Filter
and
Driver
V i d e o
PLL
Options
Selector/
Push-
Button
Audio
Amplifier
Composite
Input
Composite
Output
Audio
Input
Image
Memory
(FL ASH)
Video
Switch/
S o u n d
Trap
RF
Modulators
RF
O u t p u t
The incoming video is digitized and processed by the TVP5150A using a
14.318MHz reference crystal to the ITU-601 (formerly known as CCIR601)
specification. All internal timing is generated using this crystal. The video is quantized,
processed for brightness, contrast, chroma gain and hue, among others, and output at
the ITU rate of 27MHz on an 8 bit, time multiplexed bus, with alternating luma and
chroma samples. No other signals are required from this circuit as the ITU
specification describes a method for encrypting the horizontal and vertical timing
information directly into the digital data using timing reference makers, or TRS codes.
A brief description of the ITU-601/656 specification is as follows:
Fundamental quantization frequency: 13.5MHz
Pixel Resolution: 720 H x 486 V NTSC / 720 H x 576 PAL
Image Aspect Ratio: 4:3
Pixel Aspect Ratio: 1.1 NTSC / 0.9 PAL
Horizontal Frequency: 15,734 Hz NTSC / 15,625 Hz PAL
Vertical Frequency: 29.97 Hz NTSC / 25 Hz PAL
Clocks per Line: 1716 NTSC / 1728 PAL (27MHz clock)
Clocks per Frame: 900900 NTSC / 1080000 PAL (27 MHz clock)
Introduction
14
