Theory of Operation
In order to convert between different video standards of the same frame rate, only
spatial correction is required. Spatial correction involves changing the resolution, size
and aspect ratio of the incoming video to the output video format. This can be easily
achieved through standard digital methods utilizing scalers and FIR filters. This will be
discussed in detail.
It was decided that no off the shelf components existed that would provide the
desired functionality, so a FieldProgrammableGateArray, or FPGA, was chosen to
provide all the digital functionality. By adding input/output circuitry, memory, and
ancillary circuitry to the FPGA, the entire system could be realized. The basic
building blocks to the design are; FPGA, video decoder (ADC), video DAC, RF
modulators, image FLASH memory, audio amplifier, and multiple power supplies. A
brief description of each part follows:
FPGA:
Xilinx XC3S100E-4VQ100 (XC3S250E-4VQ100)
100K gate equivalent (250K gate equivalent)
72Kb Block RAM (216K Block RAM)
1.2V Core / 2.5V Aux / 3.3V I/O
(number is parenthesis are for SCRF405A-NTSC only)
Video Decoder:
TI TVP5150A
9bit ADC’s, 2X Over-Sampled
Line Locked Clock
4 Line Adaptive Comb Filter
Multiplexed 8bit YCrCb output bus
Video DAC:
Proprietary Design
10bit effective DAC
35 MSPS maximum conversion rate
56 dB SNR
RF Modulators: Freescale MC44BS373CA
(One for video and FM audio, one for AM audio)
30-880MHz Frequency Range
Automatic Black Level Clamping
76dB
μ
V Output Level
Image Memory: Atmel AT49BV040B-VI
512K X 8 FLASH ROM
Introduction
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