RTX-24EM
User guide
The technical characteristics can change without notice. AUR°EL S.p.A doesn’t assume the responsibility to the damages caused by an improper use of the device.
AUR°EL S.p.A.
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problems using an 8-bit wide SPI interface. Each change to MOSI is latched on the rising edge of SCK, and
each change to MISO is available on the falling edge of SCK. A timing diagram is shown in Figure 2.
Complete timing specifications are given in Table .
Figure 2: SPI timing diagram
Symbol
Parameters
Min
Max
Units
t
DS
MOSI to SCK Setup
20
ns
t
DH
SCK to MOSI hold
20
ns
t
SD
SS to MISO Valid
30
ns
t
CD
SCK to MISO Valid
30
ns
t
SCKL
SCK low time
40
ns
t
SCKH
SCK high time
40
ns
f
sck
SCK frequency
0
10
MHz
t
CS
SS to SCK Setup
20
ns
t
CH
SCK to SS Hold
20
ns
t
CSWH
SS Inactive Time
20
ns
t
CZ
SS to MISO High Z
30
ns
Table 7: SPI timing values
For each SPI command, MISO will always give three status bits on the first three SCK cycles.
•
As soon as SS goes high, the first status bit (Status[2]) is available on the MISO terminal. This bit is
called “Previous_FIFO_Order_Pending” and is high when the microcontroller has not yet processed
the previous FIFO order. This process takes a maximum of 8 clock cycles and starts on the falling
edge of the SS signal.
