AUREL RTX-24EM User Manual Download Page 2

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RTX-24EM

User guide

The technical characteristics can change without notice. AUR°EL S.p.A doesn’t assume the responsibility to the damages caused by an improper use of the device.

AUR°EL S.p.A.

Via Foro dei Tigli, 4 - 47015 Modigliana (FC) – ITALY 12/11/2019 - Rev. B

Tel.: +390546941124 – Fax: +390546941660 Page 2

http://www.aurel.it

8.1

SPI operations ........................................................................................................................... 13

8.2

SPI Commands .......................................................................................................................... 15

Programming interface ................................................................................................................. 19

9.1

RAM2, RAM1 reset .................................................................................................................... 19

9.2

RAM2 Initialization ................................................................................................................... 19

9.3

Internal PTAT current auto calibration ....................................................................................... 19

9.4

VCO auto calibration ................................................................................................................. 20

9.5

Channel Data Rate .................................................................................................................... 21

9.5.1

Bit stuffing ........................................................................................................................... 21

9.6

RF operating frequency ............................................................................................................. 22

9.7

Address byte ............................................................................................................................. 22

9.8

TX Power level .......................................................................................................................... 23

9.9

Packet (TX and RX) payload ....................................................................................................... 23

9.9.1

Mode payload size in the header ........................................................................................... 23

9.9.2

Mode payload size in RAM2 ................................................................................................... 23

9.10

Register TXFIFO and RXFIFO ................................................................................................... 24

9.11

Received Signal Strength Indicator (RSSI) ............................................................................... 24

9.12

Frequency error register : DFT_Mes[7:0] ................................................................................ 25

Transmission programming flow ................................................................................................ 25

10.1

Transmission flow, mode payload size defined in header ........................................................ 25

10.2

Transmission flow, mode payload size defined in RAM2 ......................................................... 26

Reception programming flow .................................................................................................... 27

11.1

Reception flow, mode payload size defined in header ............................................................ 27

11.2

Reception flow, mode payload size defined in RAM2 .............................................................. 28

RAM2 Registers ......................................................................................................................... 29

RF Packet format ....................................................................................................................... 37

Revision History ........................................................................................................................ 38

Summary of Contents for RTX-24EM

Page 1: ...ntents 1 General description 3 1 1 Features 3 2 RTX 24EM pin out 4 3 Reference Documentation 5 4 European Reference Standards 5 5 Overview 5 5 1 RF transceiver 6 5 1 1 Frequency synthesizer Phase Locked Loop PLL 6 5 1 2 Receiver 6 5 1 3 Transmitter 6 6 Electrical characteristics 9 6 1 General Operating Conditions 9 6 2 Supply currents on Vcc 9 6 3 RF characteristics 10 7 Functional modes 11 7 1 Po...

Page 2: ...l Data Rate 21 9 5 1 Bit stuffing 21 9 6 RF operating frequency 22 9 7 Address byte 22 9 8 TX Power level 23 9 9 Packet TX and RX payload 23 9 9 1 Mode payload size in the header 23 9 9 2 Mode payload size in RAM2 23 9 10 Register TXFIFO and RXFIFO 24 9 11 Received Signal Strength Indicator RSSI 24 9 12 Frequency error register DFT_Mes 7 0 25 10 Transmission programming flow 25 10 1 Transmission f...

Page 3: ...ntroller The EM9209 provides two communication modes with normal sensitivity NS or high sensitivity HS and programmable bit rate from 1 5kbps to 72kbps The RTX 24EM module is pin to pin compatible with Aurel previous models XTR CYP 2 4 GHz XTR VF 2 4 LP XTR VF 2 4PA LNA and XTR VF 2 4 HP The RTX 24EM module is available in the following variants Aurel Code Technical name reference Description 6502...

Page 4: ...onnection signal for external host microcontroller tive low from the external host microcontroller to the radio module forced to low level the device is resetted and in power down mode Master Out Slave In SPI signal from the external host microcontroller to the radio module Slave Select signal active high from external host microcontroller to the radio module from the external host microcontroller...

Page 5: ...inst short circuits The usage of the transceiver is foreseen inside enclosures that assure the overcoming of the rule EN 61000 4 2 not directly applicable to the module itself This device is compliant with EN 62479 connected to the electromagnetic field human exposition 5 Overview The EM9209 is a low power low voltage single chip 2 4GHz RF transceiver ideal for battery operated wireless applicatio...

Page 6: ...low 5 1 1 Frequency synthesizer Phase Locked Loop PLL The frequency synthesizer provides an accurate low jitter 100 dBc 1MHz offset 2 4GHz RF signal used for both up conversion in Transmit mode and down conversion in Receive mode Up to 20 different RF channel frequencies can be synthesized in high sensitivity mode Additionally the PLL supports direct FSK modulation for use in the Transmit mode An ...

Page 7: ...ntroller drives an interrupt pin IRQ which can be programmed to indicate the status that a packet has been sent or received or that auto calibration has finished This controller to complete other operations or even enter its own low power The RAM memories are reset through internal POR Figure 2 Digital interface controller is the central digital control system of the EM9209 It manages all RAM2 reg...

Page 8: ... 2 1 2 In Auto calibration mode The center frequency of the VCO is tuned for a chosen channel frequency The result of the auto calibration is directly written in the VCO center frequency register VCO_Code 3 0 5 2 1 3 In Standby mode The EM9209 control registers RAM2 can be read or written 5 2 1 4 In RAM2 initialization mode The EM9209 configures it s RAM2 to default value and sets IRQ pin high whe...

Page 9: ...currents on Vcc Operating Mode Notes Symbol Conditions Min Typ Max Unit Power Down ICC_PWDOWN ENABLE Pin 10 or nRESET Pin 4 0 1 µA Standby ICC_STDBY ENABLE Pin 10 or nRESET Pin 4 1 and 26MHz crystal oscillator disabled 140 µA Auto calibration IAUTOCAL Auto calibration mode 4 2 mA Transmit 1 2 ICC_TX3 POUT 1 1 dBm 2440MHz 11 mA ICC_TX7 POUT 10 dBm 2440MHz 36 mA Receive Normal sensitivity 2 ICC_RXNS...

Page 10: ...48 kbps NS 72 1 2 DR7 72 kbps Channel spacing FCHW 4 MHz Transmitter Operation RF Output power on UFL connector RTX 24EM AE H and RTX 24EM AE V versions Power level 7 3 PRF7 10 dBm Power level 6 3 PRF6 9 dBm Power level 5 3 PRF5 6 dBm Power level 4 3 PRF4 2 5 dBm Power level 3 3 PRF3 1 dBm Power level 2 3 PRF2 3 dBm Power level 1 3 PRF1 10 dBm E R P RF power RTX 24EM AI H and RTX 24EM AI V version...

Page 11: ... doesn t assume the responsibility to the damages caused by an improper use of the 47015 Modigliana FC ITALY Fax 390546941660 Sensitivity NS Normal Sensitivity In case of more than 4 consecutive identical symbols bit stuffing can reduce this data rate from 100 down to 80 of this value for more detailed power amplifier settings operational modes of the RTX 24EM module An example state diagram is gi...

Page 12: ...e 6 7 4 Auto cal VCO center frequency The RTX 24EM frequency synthesizer has an Auto calibration mode that must be run periodically by the host microcontroller This keeps the channel frequency and FSK modulator operating within specification Analog components in this block are sensitive to temperature variation therefore performance may degrade or the link may fail if not run periodically Typicall...

Page 13: ...our wires are SS Slave Select SCK Serial Clock MOSI Serial data in to RTX 24EM MISO Serial data out of RTX 24EM The RTX 24EM has a programmable interrupt pin IRQ All internal enables signals and parameters of the RTX 24EM are mapped in a small 16x12 bits memory called RAM2 RAM2 can directly be accessed through SPI and no crystal clock is required 8 1 SPI operations The SPI interface is used to rea...

Page 14: ...SPI timing diagram Symbol Parameters Min Max Units tDS MOSI to SCK Setup 20 ns tDH SCK to MOSI hold 20 ns tSD SS to MISO Valid 30 ns tCD SCK to MISO Valid 30 ns tSCKL SCK low time 40 ns tSCKH SCK high time 40 ns fsck SCK frequency 0 10 MHz tCS SS to SCK Setup 20 ns tCH SCK to SS Hold 20 ns tCSWH SS Inactive Time 20 ns tCZ SS to MISO High Z 30 ns Table 7 SPI timing values For each SPI command MISO ...

Page 15: ...luding the one being read This SPI operation works together with the internal microcontroller and is functional only when this latter has been started SPI command Start_Micro and when the master clock is active Crystal oscillator must be enabled The order is taken into account only when SS signal goes down and the RXFIFO size information are sampled when SS is low Figure 3 Timing of the SPI Read_R...

Page 16: ...ead_RAM1 This command reads the 12 bits word from the specified address 6bits of RAM1 This command will put the microcontroller on hold and reset state until last bit has been processed Write_RAM1 This command writes a 12 bits word to the specified address 6 bits of RAM1 This command will put the microcontroller on hold and reset state until last bit has been processed Read_RAM2 This command reads...

Page 17: ...nd FIFO s content could be corrupted Always first stop the micro using SPI command Stop_Micro prior to use Reset_Micro Stop_Micro This command stops the microcontroller Start_Micro This command start the microcontroller and executes the program currently stored in RAM1 Clear_IRQ Use this command to reset the IRQ signal It works only when microcontroller is running Send_TXFIFO This command will sen...

Page 18: ...m the specified ROM address to RAM1 This allows for fast initialization of the microcontroller subroutines The crystal oscillator must be enabled to perform this operation Additionally ROM_Boot command stops and resets the microcontroller ROM_Boot0_and_Start This command copies the 64 12 bits instructions from the ROM address 0 to RAM1 This allows for fast initialization of the microcontroller sub...

Page 19: ...ity can be monitored through Status 1 by using a simple Stop_Micro SPI command for example When Status 1 has gone low the RAM2 initialization subroutine can be executed Use SPI command Write_RAM1 with address 13 and data_write 1184 This will initialize RAM2 with RB_Inst_Dis 1 and this allows the user to manually select the subroutine to be stored in RAM1 Use SPI command ROM_Boot with argument ROM_...

Page 20: ...as a dedicated subroutine located at the ROM_Boot_Address 64 which will perform the VCO auto calibration Auto calibration frequency is set through register VcoCalibFreq 11 0 which is located in RAM1 at the address 53 It must be programmed through the SPI Write_RAM1 command to fit the required frequency operation VcoCalibFreq 11 0 is VcoCalibFreq 7 0 round 4259840 fo 1618 VcoCalibFreq 11 8 0b1011 0...

Page 21: ...rates are available Ch_Rate 2 0 000 to 011 On air bit rate kbps Ch_Rate 2 0 R_Bit_Clk 8 0 RAM2 12 11 0 1 5 000 110000000 0x180 2 99 001 011000000 0x2C0 6 02 010 001011111 0x45F 12 037 011 000101111 0x62F 24 074 100 000010111 0x817 48 15 101 000001011 0xA0B 72 22 110 000000111 0xC07 Table 8 Channel Data Rate To establish a communication both linked devices must be set to the same data rate 9 5 1 Bi...

Page 22: ...e same channel The host microcontroller can program a channel change which is validated when SPI signal SS goes down Channel spacing of 4 MHz is recommended to limit interference with other RTX 24EM devices operating on adjacent channels 9 7 Address byte For proper communication between two devices the receiving device must set the Address 7 0 register to match the transmitting device s Address 7 ...

Page 23: ...rd EN 300 440 allows maximum 10dBm RF radiated power This means that to be compliant with the standard the device with external antenna requires a 0dB antenna maximum gain for the power level 7 a 1dB antenna maximum gain for power level 6 a 4dB antenna maximum gain for power level 5 and so on Note 2 for the version with external antenna the current consumption is measured with 50 ohm load connecte...

Page 24: ...r enabled Status 1 0 Also the SPI command Reset_Micro will reset all internal TXFIFO and RXFIFO pointers to 0 9 11 Received Signal Strength Indicator RSSI A received signal strength indicator RSSI is available through the register Limit_RSSI 3 0 located in RAM2 8 3 0 A RSSI measurement can be activated in two different ways Packet RSSI The communication subroutines defined by SPI command ROM_Boot ...

Page 25: ...Send the SPI command ROM_Boot with ROM_Boot_Address 0 to perform the RAM2 initialization 5 Send the SPI command Write_RAM1 with address 13 and data write 1184 to set RB_Inst_Dis 1 6 Send the SPI command Start_Micro 7 Wait the IRQ pin to go to high this will mean that the RAM2 initialization subroutine has been executed 8 Clear IRQ using the SPI command Clear_IRQ 9 Send the SPI command ROM_Boot wit...

Page 26: ...de In this case the next packet transmission requires to execute only steps 24 to 27 Note 1 Transmission mode is started from reception mode So it is not possible to exclude that an incoming packet has triggered the IRQ before Sent Packet IRQ is activated IRQ is the same for all operational modes The SPI command Read_TXFIFO_Size and Read_RXFIFO_Size allows the user to look at both TXFIFO and RXFIF...

Page 27: ...ess 33 to perform the PTAT auto calibration 9 Send the SPI command Start_Micro 10 Wait the IRQ pin to go to high this will mean that the PTAT auto calibration subroutine has been executed 11 Clear IRQ using the SPI command Clear_IRQ 12 Use the SPI command Write_RAM2 to configure the Address byte Address 7 0 see section 9 7 13 Use the SPI command Write_RAM2 to configure the data rate R_Bit_Clk 8 0 ...

Page 28: ...K frequency is close to channel data rate correct reception operation can be corrupted SPI commands to retrieve RAM2 values such as Limit_RSSI 3 0 or DFT_Mes 7 0 should be sent immediately after IRQ signal has gone high 11 2 Reception flow mode payload size defined in RAM2 This section describes the entire flow for receiving RF data in mode payload size defined in RAM2 starting from the RTX 24EM i...

Page 29: ...alue Description VDD_Synth_En 11 1 0 VDD_Synth Voltage Regulator enable VDD_RXTX_En 10 1 0 VDD_RXTX Voltage Regulator enable Xtal_En 9 1 0 Crystal oscillator enable Reserved 8 1 0 Reserved Reserved 7 1 0 Reserved 6 1 0 Reserved 5 0 0 Div_Ck_Freq 0 4 0 0 Select the frequency on the clock output on DIV_CK Div_Ck_Freq 1 3 0 0 Reserved 2 1 0 Reserved bit Bit 2 should be set to 1 each time this registe...

Page 30: ... Reset Value Description Reserved 11 1 0 Reserved Reserved 10 0 0 Reserved 9 1 0 Reserved 8 0 0 Reserved 7 0 0 Reserved 6 0 0 Reserved 5 0 0 Reserved 4 1 0 Reserved 3 0 0 Reserved 2 1 0 Reserved 1 0 0 Reserved 0 1 0 RAM2 11 0 Address 3 Bit Default Value Reset Value Description Reserved 11 0 0 Reserved Reserved 10 0 0 Reserved 9 1 0 Reserved 8 0 0 Reserved 7 1 0 Reserved 6 1 0 Reserved 5 0 0 Reserv...

Page 31: ...re_PA 4 11 0 0 Current bias of the PA preamplifier Defines RF output power in Transmit mode I_Pre_PA 3 10 1 0 I_Pre_PA 2 9 1 0 I_Pre_PA 1 8 0 0 I_Pre_PA 0 7 1 0 Reserved 6 0 0 Reserved Reserved 5 0 0 Reserved 4 0 0 Reserved 3 0 0 Reserved 2 0 0 Reserved 1 0 0 Reserved 0 0 0 RAM2 11 0 Address 5 Bit Default Value Reset Value Description Reserved 11 0 0 Reserved Reserved 10 1 0 Reserved 9 0 0 Reserve...

Page 32: ...6 Bit Default Value Reset Value Description I_PA 4 11 0 0 Current bias of the PA Defines RF output in Transmit mode I_PA 3 10 1 0 I_PA 2 9 0 0 I_PA 1 8 1 0 I_PA 0 7 1 0 Reserved 6 0 0 Reserved Reserved 5 0 0 Reserved 4 0 0 Reserved 3 0 0 Reserved 2 0 0 Reserved 1 0 0 Reserved 0 0 0 RAM2 11 0 Address 7 Bit Default Value Reset Value Description Reserved 11 1 0 Reserved Reserved 10 0 0 Reserved 9 0 0...

Page 33: ...n Reserved 11 0 0 Reserved Reserved 10 1 0 Reserved 9 0 0 Reserved 8 0 0 Reserved 7 1 0 Reserved 6 0 0 RB_Inst_Dis 5 0 0 ROMboot Instruction Disable Reserved 4 0 0 Reserved Limit_RSSI 3 3 0 0 RSSI value Limit_RSSI 2 2 0 0 Limit_RSSI 1 1 0 0 Limit_RSSI 0 0 0 0 RAM2 11 0 Address 9 Bit Default Value Reset Value Description Reserved 11 1 0 Reserved Reserved 10 0 0 Reserved 9 1 0 Reserved 8 0 0 DFT_Mes...

Page 34: ...l it RAM2 11 0 Address 10 Bit Default Value Reset Value Description Reserved 11 0 0 Reserved Reserved 10 0 0 Reserved 9 1 0 Reserved 8 0 0 Reserved 7 1 0 Reserved 6 0 0 Reserved 5 0 0 Reserved 4 0 0 Reserved 3 0 0 Reserved 2 1 0 Reserved 1 0 0 Reserved 0 0 0 RAM2 11 0 Address 11 Bit Default Value Reset Value Description Reserved 11 0 0 Reserved Reserved 10 0 0 Reserved 9 0 0 Reserved 8 0 0 Reserve...

Page 35: ...escription Ch_Rate 2 11 0 0 Bandwidth of the normal sensitivity demodulator Ch_Rate 1 10 0 0 Ch_Rate 0 9 0 0 R_Bit_Ck 8 8 1 0 CODEC Bit clock frequency R_Bit_Ck 7 7 1 0 R_Bit_Ck 6 6 0 0 R_Bit_Ck 5 5 0 0 R_Bit_Ck 4 4 0 0 R_Bit_Ck 3 3 0 0 R_Bit_Ck 2 2 0 0 R_Bit_Ck 1 1 0 0 R_Bit_Ck 0 0 0 0 RAM2 11 0 Address 13 Bit Default Value Reset Value Description Reserved 11 0 0 Reserved Reserved 10 0 0 Reserved...

Page 36: ...alue Reset Value Description Reserved 11 0 0 Reserved Reserved 10 0 0 Frequ 4 9 0 0 Synthesizer s RF Frequency LSB s Frequ 3 8 1 0 Frequ 2 7 1 0 Frequ 1 6 1 0 Frequ 0 5 0 0 N_Pay 4 4 0 0 Payload size of the Packet N_Pay 1 N_Pay 3 3 0 0 N_Pay 2 2 0 0 N_Pay 1 1 1 0 N_Pay 0 0 1 0 RAM2 11 0 Address 15 Bit Default Value Reset Value Description Frequ 16 11 0 0 Synthesizer s RF Frequency MSB s Frequ 15 1...

Page 37: ... 5 LSB s of the header represent the payload size of the packet for payload size defined in header mode ROM_Boot_Address 320 For payload size defined in RAM2 mode ROM_Boot_Address 192 the header is not existing Payload 0 32 bytes Data In high sensitivity mode each packet contains the following information Marking Preamble 3 Address Byte Header Payload Packet information Length Description Marking ...

Page 38: ...the technical specifications and to comply with the operating conditions which characterize the certification the device must be mounted on a printed circuit taking into account the following Voltage Supply 1 The module must be powered by a low voltage safety source protected against short circuits Maximum allowed voltage variations 1 9 3 6V 2 Decoupling near the transmitter with a ceramic capacit...

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