RTX-24EM
User guide
The technical characteristics can change without notice. AUR°EL S.p.A doesn’t assume the responsibility to the damages caused by an improper use of the device.
AUR°EL S.p.A.
Via Foro dei Tigli, 4 - 47015 Modigliana (FC) – ITALY 12/11/2019 - Rev. B
Tel.: +390546941124 – Fax: +390546941660 Page 26
http://www.aurel.it
22.
Send the SPI command
ROM_Boot
with
ROM_Boot_Address = 256
for High sensitivity mode or
320
for
Normal sensitivity mode.
23.
Send the SPI command
Start_Micro
.
24.
Write the
TXFIFO
through SPI command
Write_TXFIFO
. The first byte written is the header and
contents the payload size in its 5 LSBs.
25.
Send the SPI command
Send_TXFIFO
to transmit the packet: the RTX-24EM will send the RF packet
until
TXFIFO
is empty.
26.
Wait the IRQ pin to go to high: this will mean that the RF packet transmission has been completed.
27.
Clear IRQ using the SPI command
Clear_IRQ
.
At the end of the transmission the RTX-24EM goes to reception mode therefore, if low power consumption
is required, it will be necessary to set ENABLE (Pin 10) or nRESET (Pin 4) to GND to force the RTX-24EM in
power down mode. The next packet transmission requires to execute all steps from 1 to 27.
If the low power consumption is not required, at the end of the transmission the RTX-24EM can stay in
reception mode. In this case the next packet transmission requires to execute only steps 24 to 27.
Note 1
: Transmission mode is started from reception mode. So, it is not possible to exclude that an
incoming packet has triggered the IRQ before Sent Packet IRQ is activated (IRQ is the same for all
operational modes). The SPI command
Read_TXFIFO_Size
and
Read_RXFIFO_Size
allows the user to look at
both
TXFIFO
and
RXFIFO
to determine the origin of the interrupt.
Note 2
: Transmission mode is operated by the internal microcontroller, which operates by taking control of
RAM2
and
TXFIFO
. Read and Write SPI accesses to
RAM2
will put the microcontroller on hold. If the SPI
transaction time is too long (if SCK frequency is close to channel data rate), correct transmission operation
can be corrupted. SPI commands to retrieve
RAM2
values such as
Limit_RSSI[3:0]
or
DFT_Mes[7:0]
should
be sent immediately after IRQ signal has gone high rather than after a
Send_TXFIFO
request.
10.2 Transmission flow, mode payload size defined in RAM2
This section describes the entire flow for transmitting RF data, in mode payload size in RAM2, starting from
the RTX-24EM in power down mode (ENABLE (Pin 10) or nRESET (Pin 4) = GND).
The steps are the same as described in section 10.1 excepted:
•
the payload size
N_Pay[4:0]
must be write in
RAM2
after step 12;
•
the header byte no longer defines the number of byte of the payload;
•
the
ROM_Boot_Address
must be set
= 128
for High sensitivity mode or
192
for Normal sensitivity
mode, in step 22.
