Atmel ATtiny25 Manual Download Page 184

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184

7598H–AVR–07/09

ATtiny25/45/85

25. Instruction Set Summary

Mnemonics

Operands

Description

Operation

Flags

#Clocks

ARITHMETIC AND LOGIC INSTRUCTIONS

ADD

Rd, Rr

Add two Registers

←

Rd + Rr

Z,C,N,V,H

ADC

Rd, Rr

Add with Carry two Registers

←

Rd + Rr + C

Z,C,N,V,H

ADIW

Rdl,K

Add Immediate to Word

Rdh:Rdl

←

Rdh:Rdl + K

Z,C,N,V,S

SUB

Rd, Rr

Subtract two Registers

←

Rd - Rr

Z,C,N,V,H

SUBI

Rd, K

Subtract Constant from Register

←

Rd - K

Z,C,N,V,H

SBC

Rd, Rr

Subtract with Carry two Registers

←

Rd - Rr - C

Z,C,N,V,H

SBCI

Rd, K

Subtract with Carry Constant from Reg.

←

Rd - K - C

Z,C,N,V,H

SBIW

Rdl,K

Subtract Immediate from Word

Rdh:Rdl

←

Rdh:Rdl - K

Z,C,N,V,S

AND

Rd, Rr

Logical AND Registers

←

•

Z,N,V

ANDI

Rd, K

Logical AND Register and Constant

←

•

Z,N,V

Rd, Rr

Logical OR Registers

←

Rd v Rr

Z,N,V

ORI

Rd, K

Logical OR Register and Constant

←

Rd v K

Z,N,V

EOR

Rd, Rr

Exclusive OR Registers

←

⊕

Z,N,V

COM

One’s Complement

←

0xFF

−

Z,C,N,V

NEG

Two’s Complement

←

0x00

−

Z,C,N,V,H

SBR

Rd,K

Set Bit(s) in Register

←

Rd v K

Z,N,V

CBR

Rd,K

Clear Bit(s) in Register

←

•

(0xFF - K)

Z,N,V

INC

Increment

←

Rd + 1

Z,N,V

DEC

Decrement

←

−

Z,N,V

TST

Test for Zero or Minus

←

•

Z,N,V

CLR

Clear Register

←

⊕

Z,N,V

SER

Set Register

←

0xFF

None

BRANCH INSTRUCTIONS

RJMP

Relative Jump

←

PC + k + 1

None

IJMP

Indirect Jump to (Z)

←

None

RCALL

Relative Subroutine Call

←

PC + k + 1

None

ICALL

Indirect Call to (Z)

←

None

RET

Subroutine Return

←

STACK

None

RETI

Interrupt Return

←

STACK

CPSE

Rd,Rr

Compare, Skip if Equal

if (Rd = Rr) PC

←

PC + 2 or 3

None

1/2/3

Rd,Rr

Compare

−

Z, N,V,C,H

CPC

Rd,Rr

Compare with Carry

−

Z, N,V,C,H

CPI

Rd,K

Compare Register with Immediate

−

Z, N,V,C,H

SBRC

Rr, b

Skip if Bit in Register Cleared

if (Rr(b)=0) PC

←

PC + 2 or 3

None

1/2/3

SBRS

Rr, b

Skip if Bit in Register is Set

if (Rr(b)=1) PC

←

PC + 2 or 3

None

1/2/3

SBIC

P, b

Skip if Bit in I/O Register Cleared

if (P(b)=0) PC

←

PC + 2 or 3

None

1/2/3

SBIS

P, b

Skip if Bit in I/O Register is Set

if (P(b)=1) PC

←

PC + 2 or 3

None

1/2/3

BRBS

s, k

Branch if Status Flag Set

if (SREG(s) = 1) then PC

←

PC+k + 1

None

1/2

BRBC

s, k

Branch if Status Flag Cleared

if (SREG(s) = 0) then PC

←

PC+k + 1

None

1/2

BREQ

Branch if Equal

if (Z = 1) then PC

←

PC + k + 1

None

1/2

BRNE

Branch if Not Equal

if (Z = 0) then PC

←

PC + k + 1

None

1/2

BRCS

Branch if Carry Set

if (C = 1) then PC

←

PC + k + 1

None

1/2

BRCC

Branch if Carry Cleared

if (C = 0) then PC

←

PC + k + 1

None

1/2

BRSH

Branch if Same or Higher

if (C = 0) then PC

←

PC + k + 1

None

1/2

BRLO

Branch if Lower

if (C = 1) then PC

←

PC + k + 1

None

1/2

BRMI

Branch if Minus

if (N = 1) then PC

←

PC + k + 1

None

1/2

BRPL

Branch if Plus

if (N = 0) then PC

←

PC + k + 1

None

1/2

BRGE

Branch if Greater or Equal, Signed

if (N

⊕

V= 0) then PC

←

PC + k + 1

None

1/2

BRLT

Branch if Less Than Zero, Signed

if (N

⊕

V= 1) then PC

←

PC + k + 1

None

1/2

BRHS

Branch if Half Carry Flag Set

if (H = 1) then PC

←

PC + k + 1

None

1/2

BRHC

Branch if Half Carry Flag Cleared

if (H = 0) then PC

←

PC + k + 1

None

1/2

BRTS

Branch if T Flag Set

if (T = 1) then PC

←

PC + k + 1

None

1/2

BRTC

Branch if T Flag Cleared

if (T = 0) then PC

←

PC + k + 1

None

1/2

BRVS

Branch if Overflow Flag is Set

if (V = 1) then PC

←

PC + k + 1

None

1/2

BRVC

Branch if Overflow Flag is Cleared

if (V = 0) then PC

←

PC + k + 1

None

1/2

BRIE

Branch if Interrupt Enabled

if ( I = 1) then PC

←

PC + k + 1

None

1/2

BRID

Branch if Interrupt Disabled

if ( I = 0) then PC

←

PC + k + 1

None

1/2

BIT AND BIT-TEST INSTRUCTIONS

SBI

P,b

Set Bit in I/O Register

I/O(P,b)

←

None

CBI

P,b

Clear Bit in I/O Register

I/O(P,b)

←

None

LSL

Logical Shift Left

Rd(n+1)

←

Rd(n), Rd(0)

←

Z,C,N,V

LSR

Logical Shift Right

Rd(n)

←

Rd(n+1), Rd(7)

←

Z,C,N,V

ROL

Rotate Left Through Carry

Rd(0)

←

C,Rd(n+1)

←

Rd(n),C

←

Rd(7)

Z,C,N,V

Summary of Contents for ATtiny25

Page 1: ...ammable Dead Time Generator Universal Serial Interface with Start Condition Detector 10 bit ADC 4 Single Ended Channels 2 Differential ADC Channel Pairs with Programmable Gain 1x 20x Programmable Watc...

Page 2: ...erful instructions in a single clock cycle the ATtiny25 45 85 achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed 1 2 3 4...

Page 3: ...cient while achieving throughputs up to ten times faster than con ventional CISC microcontrollers PROGRAM COUNTER INTERNAL OSCILLATOR WATCHDOG TIMER STACK POINTER PROGRAM FLASH SRAM MCU CONTROL REGIST...

Page 4: ...serial interface by a conventional non volatile memory programmer or by an On chip boot code running on the AVR core The ATtiny25 45 85 AVR is supported with a full suite of program and system develo...

Page 5: ...than the minimum pulse length will generate a reset even if the clock is not running The minimum pulse length is given in Table 8 1 on page 37 Shorter pulses are not guaranteed to generate a reset 3 A...

Page 6: ...le cycle Arithmetic Logic Unit ALU operation In a typ ical ALU operation two operands are output from the Register File the operation is executed and the result is stored back in the Register File in...

Page 7: ...the Interrupt Vector address the higher the priority The I O memory space contains 64 addresses for CPU peripheral functions as Control Regis ters SPI and other I O functions The I O memory can be ac...

Page 8: ...to a bit in a register in the Register File by the BLD instruction Bit 5 H Half Carry Flag The Half Carry Flag H indicates a Half Carry in some arithmetic operations Half Carry is useful in BCD arithm...

Page 9: ...ng Registers Most of the instructions operating on the Register File have direct access to all registers and most of them are single cycle instructions As shown in Figure 4 2 each register is also ass...

Page 10: ...the data SRAM must be defined by the program before any subroutine calls are executed or interrupts are enabled The Stack Pointer must be set to point above 0x60 The Stack Pointer is decremented by on...

Page 11: ...ion register Figure 4 5 Single Cycle ALU Operation 4 8 Reset and Interrupt Handling The AVR provides several different interrupt sources These interrupts and the separate Reset Vector each have a sepa...

Page 12: ...the Global Interrupt Enable bit is set and will then be executed by order of priority The second type of interrupts will trigger as long as the interrupt condition is present These interrupts do not n...

Page 13: ...mories This section describes the different memories in the ATtiny25 45 85 The AVR architecture has two main memory spaces the Data memory and the Program memory space In addition the ATtiny25 45 85 f...

Page 14: ...to R31 feature the indirect addressing pointer registers The direct addressing reaches the entire data space The Indirect with Displacement mode reaches 63 address locations from the base address giv...

Page 15: ...ess times for the EEPROM are given in Table 5 1 A self timing function however lets the user software detect when the next byte can be written If the user code contains instruc tions that write the EE...

Page 16: ...EPROM Data Register EEDR Bits 7 0 EEDR7 0 EEPROM Data For the EEPROM write operation the EEDR Register contains the data to be written to the EEPROM in the address given by the EEAR Register For the E...

Page 17: ...EEPE will have no effect When EEMPE has been written to one by software hardware clears the bit to zero after four clock cycles Bit 1 EEPE EEPROM Program Enable The EEPROM Program Enable Signal EEPE i...

Page 18: ...Power up 5 3 8 Erase To erase a byte the address must be written to EEAR If the EEPMn bits are 0b01 writing the EEPE within four cycles after EEMPE is written will trigger the erase operation only pro...

Page 19: ...ata r16 to data register out EEDR r16 Write logical one to EEMWE sbi EECR EEMWE Start eeprom write by setting EEWE sbi EECR EEWE ret C Code Example void EEPROM_write unsigned char ucAddress unsigned c...

Page 20: ...corruption can easily be avoided by following this design recommendation Keep the AVR RESET active low during periods of insufficient power supply voltage This can be done by enabling the internal Bro...

Page 21: ...me of the Status Flags are cleared by writing a logical one to them Note that the CBI and SBI instructions will only operate on the specified bit and can therefore be used on registers contain ing suc...

Page 22: ...ral Clock Generation clkPCK The internal PLL in ATtiny25 45 85 generates a clock frequency that is 8x multiplied from a source input The source of the PLL input clock is the output of the internal RC...

Page 23: ...ecution starts When the CPU starts from reset there is an additional delay allowing the power to reach a stable level before commencing normal operation The Watchdog Oscillator is used for timing this...

Page 24: ...nator in use the amount of stray capacitance and the electromagnetic noise of the environment Some initial guidelines for choosing capacitors for use with crystals are given in Table 6 3 For ceramic r...

Page 25: ...ed start up times are determined by the SUT fuses as shown in Table 6 5 Notes 1 These options should only be used if frequency stability at start up is not important for the application Table 6 4 Star...

Page 26: ...ned by the SUT Fuses as shown in Table 6 7 Note 1 The device is shipped with this option selected 6 6 1 Oscillator Calibration Register OSCCAL Bits 7 0 CAL7 0 Oscillator Calibration Value Writing the...

Page 27: ...he next can lead to unpredicatble behavior Changes in OSCCAL should not exceed 0x20 for each calibration It is required to ensure that the MCU is kept in Reset during such changes in the clock frequen...

Page 28: ...e 128 kHz internal Oscillator is a low power Oscillator providing a clock of 128 kHz The fre quency is nominal at 3V and 25 C This clock may be select as the system clock by programming the CKSEL Fuse...

Page 29: ...is only updated when the other bits in CLKPR are simultaniosly written to zero CLKPCE is cleared by hardware four cycles after it is written or when the CLKPS bits are written Rewriting the CLKPCE bit...

Page 30: ...he clock system and that no intermediate frequency is higher than neither the clock frequency corresponding to the previous setting nor the clock frequency corresponding to the new setting The ripple...

Page 31: ...ate sleep mode 7 1 MCU Control Register MCUCR The MCU Control Register contains control bits for power management Bit 7 BODS BOD Sleep BOD disable functionality is available in some devices only See L...

Page 32: ...ode is entered 7 3 ADC Noise Reduction Mode When the SM1 0 bits are written to 01 the SLEEP instruction makes the MCU enter ADC Noise Reduction mode stopping the CPU but allowing the ADC the external...

Page 33: ...module which is done by clearing the bit in PRR puts the module in the same state as before shutdown Module shutdown can be used in Idle mode and Active mode to significantly reduce the overall power...

Page 34: ...on page 111 for details on ADC operation 7 7 2 Analog Comparator When entering Idle mode the Analog Comparator should be disabled if not used When entering ADC Noise Reduction mode the Analog Compara...

Page 35: ...er to Digital Input Disable Register 0 DIDR0 on page 110 for details 8 System Control and Reset 8 1 Resetting the AVR During reset all I O Registers are set to their initial values and the program sta...

Page 36: ...y voltage A Power on Reset POR circuit ensures that the device is reset from Power on Reaching the Power on Reset threshold voltage invokes the delay counter which determines how long the device is ke...

Page 37: ...rate a reset When the applied signal reaches the Reset Threshold Voltage VRST on its positive edge the delay counter starts the MCU after the Time out period tTOUT has expired Symbol Parameter Min Typ...

Page 38: ...some devices For devices where this is the case the device is tested down to VCC VBOT during the production test This guar antees that a Brown out Reset will occur before VCC drops to a voltage where...

Page 39: ...it will only detect a drop in VCC if the voltage stays below the trigger level for lon ger than tBOD given in Table 8 1 Figure 8 5 Brown out Reset During Operation 8 6 Watchdog Reset When the Watchdog...

Page 40: ...CUSR as early as possible in the program If the register is cleared before another reset occurs the source of the reset can be found by examining the Reset Flags 8 8 Internal Voltage Reference ATtiny2...

Page 41: ...instead of a reset This can be very helpful when using the Watchdog to wake up from Power down To prevent unintentional disabling of the Watchdog or unintentional change of time out period two differe...

Page 42: ...Watchdog will not be disabled Once written to one hardware will clear this bit after four clock cycles Refer to the description of the WDE bit for a Watchdog disable procedure This bit must also be se...

Page 43: ...lead to a new watchdog reset To avoid this situation the application software should always clear the WDRF flag and the WDE control bit in the initialization routine Bits 5 2 0 WDP3 0 Watchdog Timer...

Page 44: ...DE bit to one without any restriction A timed sequence is needed when disabling an enabled Watch dog Timer To disable an enabled Watchdog Timer the following procedure must be followed 1 In the same o...

Page 45: ...Ttiny25 45 85 For a general explanation of the AVR interrupt handling refer to Reset and Interrupt Handling on page 11 9 1 Interrupt Vectors in ATtiny25 45 85 Table 9 1 Reset and Interrupt Vectors Vec...

Page 46: ...Main program start 0x0010 ldi r17 high RAMEND Tiny85 has also SPH 0x0011 out SPL r16 Set Stack Pointer to top of RAM 0x0012 out SPH r17 Tiny85 has also SPH 0x0013 sei Enable interrupts 0x0014 instr x...

Page 47: ...logic one to a bit in the PINx Register will result in a toggle in the correspond ing bit in the Data Register In addition the Pull up Disable PUD bit in MCUCR disables the pull up function for all p...

Page 48: ...ull up resistor is activated To switch the pull up resistor off PORTxn has to be written logic zero or the pin has to be configured as an output pin The port pins are tri stated when reset condition b...

Page 49: ...10 2 4 Reading the Pin Value Independent of the setting of Data Direction bit DDxn the port pin can be read through the PINxn Register bit As shown in Figure 10 2 the PINxn Register bit and the preced...

Page 50: ...When reading back a software assigned pin value a nop instruction must be inserted as indi cated in Figure 10 4 The out instruction sets the SYNC LATCH signal at the positive edge of the clock In thi...

Page 51: ...abled SLEEP is active also for these pins SLEEP is also overridden by various other alternate functions as described in Alternate Port Functions on page 52 If a logic high level one is present on an a...

Page 52: ...the port pin control signals from the simplified Figure 10 2 can be overridden by alternate functions The overriding signals may not be present in all port pins but the figure serves as a generic desc...

Page 53: ...n Register bit DDOV Data Direction Override Value If DDOE is set the Output Driver is enabled disabled when DDOV is set cleared regardless of the setting of the DDxn Register bit PVOE Port Value Overr...

Page 54: ...Pin Change Interrupt 6 Serial Data Output Analog Comparator Positive Input Timer Counter0 Output Compare and PWM Output A Timer Counter1 Inverted Output Compare and PWM Output A USI Data Input three...

Page 55: ...or the Timer Counter1 Compare Match B when configured as an output DDB3 set The OC1B pin is also the inverted output pin for the PWM mode timer function PCINT3 Pin Change Interrupt source 3 Port B Bit...

Page 56: ...a Master the data direction of this pin is controlled by DDB0 When the pin is forced by the SPI to be an input the pull up can still be controlled by the PORTB0 bit AIN0 Analog Comparator Positive In...

Page 57: ...2D ADC3D DI PCINT5 Input PCINT4 Input PCINT3 Input AIO RESET Input ADC0 Input ADC2 Input ADC3 Input Table 10 5 Overriding Signals for Alternate Functions in PB3 PB0 Signal Name PB2 SCK ADC1 T0 USCK SC...

Page 58: ...igger as long as the pin is held low Note that recognition of falling or rising edge interrupts on INT0 requires the presence of an I O clock described in Clock Systems and their Distribution on page...

Page 59: ...terrupt is enabled The Interrupt Sense Control0 bits 1 0 ISC01 and ISC00 in the MCU Control Register MCUCR define whether the external interrupt is activated on rising and or fall ing edge of the INT0...

Page 60: ...ne If the I bit in SREG and the PCIE bit in GIMSK are set one the MCU will jump to the cor responding Interrupt Vector The flag is cleared when the interrupt routine is executed Alternatively the flag...

Page 61: ...bit Timer Counter Register Description on page 72 Figure 12 1 8 bit Timer Counter Block Diagram 12 1 1 Registers The Timer Counter TCNT0 and Output Compare Registers OCR0A and OCR0B are 8 bit registe...

Page 62: ...lso used extensively throughout the document 12 2 Timer Counter Clock Sources The Timer Counter can be clocked by an internal or an external clock source The clock source is selected by the Clock Sele...

Page 63: ...counts and how waveforms are generated on the Output Compare output OC0A For more details about advanced counting sequences and waveform generation see Modes of Opera tion on page 66 The Timer Counte...

Page 64: ...s dis abled the CPU will access the OCR0x directly 12 4 1 Force Output Compare In non PWM waveform generation modes the match output of the comparator can be forced by writing a one to the Force Outpu...

Page 65: ...de COM0x1 0 bits have two functions The Waveform Generator uses the COM0x1 0 bits for defining the Output Compare OC0x state at the next Compare Match Also the COM0x1 0 bits control the OC0x pin outpu...

Page 66: ...the output should be set cleared or toggled at a Compare Match See Compare Match Output Unit on page 65 For detailed timing information refer to Figure 12 8 Figure 12 9 Figure 12 10 and Figure 12 11...

Page 67: ...e OC0A value will not be visible on the port pin unless the data direction for the pin is set to output The waveform generated will have a maximum frequency of fOC0 fclk_I O 2 when OCR0A is set to zer...

Page 68: ...ion of PWM waveforms on the OC0x pins Setting the COM0x1 0 bits to two will produce a non inverted PWM and an inverted PWM output can be generated by setting the COM0x1 0 to three Setting the COM0A1 0...

Page 69: ...pare Output mode the Output Compare OC0x is cleared on the Compare Match between TCNT0 and OCR0x while upcounting and set on the Compare Match while down counting In inverting Output Compare mode the...

Page 70: ...s when generating a PWM waveform output in the phase correct PWM mode If the OCR0A is set equal to BOTTOM the output will be continuously low and if set equal to MAX the output will be continuously hi...

Page 71: ...des and OCF0A in all modes except CTC mode and PWM mode where OCR0A is TOP Figure 12 10 Timer Counter Timing Diagram Setting of OCF0x with Prescaler fclk_I O 8 Figure 12 11 shows the setting of OCF0A...

Page 72: ...ed to the pin the function of the COM0A1 0 bits depends on the WGM02 0 bit setting Table 12 1 shows the COM0A1 0 bit functionality when the WGM02 0 bits are set to a normal or CTC mode non PWM Table 1...

Page 73: ...utput driver When OC0B is connected to the pin the function of the COM0B1 0 bits depends on the WGM02 0 bit setting Table 12 1 shows the COM0A1 0 bit functionality when the WGM02 0 bits are set to a n...

Page 74: ...Mode Combined with the WGM02 bit found in the TCCR0B Register these bits control the counting sequence of the counter the source for maximum TOP counter value and what type of wave form generation to...

Page 75: ...are B The FOC0B bit is only active when the WGM bits specify a non PWM mode However for ensuring compatibility with future devices this bit must be set to zero when TCCR0B is written when operating in...

Page 76: ...he TCNT0 Register blocks removes the Compare Match on the following timer clock Modifying the counter TCNT0 while the counter is running introduces a risk of missing a Compare Match between TCNT0 and...

Page 77: ...the I bit in the Status Register is set the Timer Counter0 Compare Match A interrupt is enabled The corresponding interrupt is executed if a Compare Match in Timer Counter0 occurs i e when the OCF0A b...

Page 78: ...ogic one to the flag When the SREG I bit TOIE0 Timer Counter0 Overflow Interrupt Enable and TOV0 are set the Timer Counter0 Overflow interrupt is executed The setting of this flag is dependent of the...

Page 79: ...has been applied to the T0 pin to the counter is updated Enabling and disabling of the clock input must be done when T0 has been stable for at least one system clock cycle otherwise it is a risk that...

Page 80: ...Reset signal asserted This ensures that the Timer Counter is halted and can be configured without the risk of advanc ing during configuration When the TSM bit is written to zero the PSR0 bit is clear...

Page 81: ...ounter 1 synchronization register block diagram and syn chronization delays in between registers Note that all clock gating details are not shown in the figure The Timer Counter1 register values go th...

Page 82: ...t two edges of the PCK when the system clock is high If the frequency of the system clock is too high it is a risk that data or control values are lost The following Figure 14 3 shows the block diagra...

Page 83: ...nd OC1B are not connected in normal mode In PWM mode OCR1A and OCR1B provide the data values against which the Timer Counter value is compared Upon compare match the PWM outputs OC1A OC1A OC1B OC1B ar...

Page 84: ...alternative function to an I O port the corresponding direction control bit must be set one in order to control an output pin Note that OC1A is not connected in normal mode In PWM mode these bits hav...

Page 85: ...ust be set one in order to control an output pin Note that OC1B is not connected in normal mode In PWM mode these bits have different functions Refer to Table 14 4 on page 90 for a detailed descriptio...

Page 86: ...1 Prescaler Reset Timer Counter1 When this bit is set one the Timer Counter prescaler TCNT1 is unaffected will be reset The bit will be cleared by hardware after the operation is performed Writing a z...

Page 87: ...ction in normal mode and PWM mode 14 1 7 Timer Counter Interrupt Mask Register TIMSK Bit 7 Res Reserved Bit This bit is a reserved bit in the ATtiny25 45 85 and always reads as zero Bit 6 OCIE1A Timer...

Page 88: ...Res Reserved Bit This bit is a reserved bit in the ATtiny25 45 85 and always reads as zero Bit 6 OCF1A Output Compare Flag 1A The OCF1A bit is set one when compare match occurs between Timer Counter1...

Page 89: ...s read as zero Bit 2 PCKE PCK Enable The PCKE bit change the Timer Counter1 clock source When it is set the asynchronous clock mode is enabled and fast 64 MHz or 32 MHz in Low Speed Mode PCK clock is...

Page 90: ...e value specified in the output compare register OCR1C and starting from 00 up again A compare match with OC1C will set an overflow interrupt flag TOV1 after a synchronization delay following the comp...

Page 91: ...o the OCR1C value and the TCNT1 is reset to 00 The Timer Overflow Interrupt1 is executed when TOV1 is set provided that Timer Overflow Interrupt and global interrupts are enabled This also applies to...

Page 92: ...0 199 7 6 50 kHz PCK 8 0100 159 7 3 60 kHz PCK 8 0100 132 7 1 70 kHz PCK 4 0011 228 7 8 80 kHz PCK 4 0011 199 7 6 90 kHz PCK 4 0011 177 7 5 100 kHz PCK 4 0011 159 7 3 110 kHz PCK 4 0011 144 7 2 120 kH...

Page 93: ...as shown in Figure 46 There is a dedicated prescaler in front of the Dead Time Generator that can divide the Timer Counter1 clock PCK or CK by 1 2 4 or 8 This provides for large range of dead times t...

Page 94: ...escaler register DTPS1 is a 2 bit read write register Bits 1 0 DTPS1 Timer Counter1 Dead Time Prescaler register 1 The dedicated Dead Time prescaler in front of the Dead Time Generator can divide the...

Page 95: ...ead time value register Bis an 8 bit read write register The dead time delay of is adjusted by the dead time value register DT1B The register consists of two fields DT1BH3 0 and DT1BL3 0 one for each...

Page 96: ...and bit locations are listed in the USI Register Descriptions on page 103 Figure 16 1 Universal Serial Interface Block Diagram The 8 bit Shift Register is directly accessible via the data bus and cont...

Page 97: ...e wire mode is compliant to the Serial Peripheral Interface SPI mode 0 and 1 but does not have the slave select SS pin functionality However this feature can be implemented in software if necessary Pi...

Page 98: ...y specific order but both must be at least one half USCK cycle before point C where the data is sampled This must be done to ensure that the data setup requirement is satisfied The 4 bit counter is re...

Page 99: ...the USI Counter Overflow Flag and the USI counter value The fourth and fifth instruction set Three wire mode positive edge Shift Register clock count at USITC strobe and toggle USCK The loop is repea...

Page 100: ...figured as input in the DDR Register The value stored in register r16 prior to the function is called is transferred to the master device and when the transfer is completed the data received from the...

Page 101: ...practical use in this mode The slave can insert wait states at start or end of transfer by forcing the SCL clock low This means that the Master must always check if the SCL line was actually released...

Page 102: ...the Slave is addressed it holds the SDA line low during the acknowledgment cycle before holding the SCL line low again i e the Counter Register must be set to 14 before releasing SCL at D Depending o...

Page 103: ...ister USIDR the Serial Register can be accessed directly If a serial clock occurs at the same cycle the register is written the register will contain the value written and no shift is performed A left...

Page 104: ...sleep modes Bit 6 USIOIF Counter Overflow Interrupt Flag This flag is set one when the 4 bit counter overflows i e at the transition from 15 to 0 An interrupt will be generated when the flag is set w...

Page 105: ...there is a pending inter rupt when the USISIE and the Global Interrupt Enable Flag is set to one this will immediately be executed Refer to the USISIF bit description on page 104 for further details...

Page 106: ...up is controlled by the PORT bit The Data Input DI and Serial Clock USCK pins do not affect the normal port operation When operating as master clock pulses are software generated by toggling the PORT...

Page 107: ...Port Pin Writing a one to this bit location toggles the USCK SCL value either from 0 to 1 or from 1 to 0 The toggling is independent of the setting in the Data Direction Register but if the PORT value...

Page 108: ...RB Bit 6 ACME Analog Comparator Multiplexer Enable When this bit is written logic one and the ADC is switched off ADEN in ADCSRA is zero the ADC multiplexer selects the negative input to the Analog Co...

Page 109: ...interrupt routine is executed if the ACIE bit is set and the I bit in SREG is set ACI is cleared by hardware when executing the corresponding inter rupt handling vector Alternatively ACI is cleared b...

Page 110: ...e input to the Analog Comparator 17 3 1 Digital Input Disable Register 0 DIDR0 Bits 1 0 AIN1D AIN0D AIN1 AIN0 Digital Input Disable When this bit is written logic one the digital input buffer on the A...

Page 111: ...ich allows one differential voltage input and four single ended voltage inputs constructed from the pins of Port B The differential input PB3 PB4 or PB2 PB5 is equipped with a programmable gain stage...

Page 112: ...2 or ADC0 can be selected as positive input and ADC0 ADC1 ADC2 or ADC3 can be selected as negative input to the differential gain amplifier If differential channels are selected the differential gain...

Page 113: ...s lost When ADCH is read ADC access to the ADCH and ADCL Registers is re enabled The ADC has its own interrupt which can be triggered when a conversion completes When ADC access to the data registers...

Page 114: ...ADCSRA to one ADSC can also be used to determine if a conversion is in progress The ADSC bit will be read as one during a conversion independently of how the conversion was started 18 4 Prescaling and...

Page 115: ...st conversion When a conversion is complete the result is written to the ADC Data Registers and ADIF is set In Single Conversion mode ADSC is cleared simultaneously The software may then set ADSC agai...

Page 116: ...sion Next Conversion 3 Sample Hold MUX and REFS Update Conversion Complete MUX and REFS Update 1 2 3 4 5 6 7 8 9 10 11 12 13 Sign and MSB of Result LSB of Result ADC Clock Trigger Source ADIF ADCH ADC...

Page 117: ...the next conversion is based on the old or the new settings ADMUX can be safely updated in the following ways a When ADATE or ADEN is cleared b During conversion minimum one ADC clock cycle after the...

Page 118: ...errupt request will be generated when the ADC conversion completes The CPU will remain in active mode until a new sleep command is executed Note that the ADC will not be automatically turned off when...

Page 119: ...Use the ADC noise canceler function to reduce induced noise from the CPU c If any port pins are used as digital outputs it is essential that these do not switch while a conversion is in progress 18 6...

Page 120: ...justing for offset and gain error the INL is the maximum deviation of an actual transition compared to an ideal transition for any code Ideal value 0 LSB Figure 18 11 Integral Non linearity INL Differ...

Page 121: ...lt Registers ADCL ADCH The form of the conversion result depends on the type of the conversio as there are three types of conversions single ended conversion unipolar differential conversion and bipol...

Page 122: ...ne bit of the converter dynamic range Then if the user wants to perform the conversion with the maximum dynamic range the user can perform a quick polarity check of the result and use the unipolar dif...

Page 123: ...F higher than VCC 1V as a voltage reference is not recommended as this will affect the ADC accuracy Bit 5 ADLAR ADC Left Adjust Result The ADLAR bit affects the presentation of the ADC conversion resu...

Page 124: ...DC is turned off Turning the ADC off while a conversion is in progress will terminate this conversion Bit 6 ADSC ADC Start Conversion In Single Conversion mode write this bit to one to start each conv...

Page 125: ...Interrupt Flag This bit is set when an ADC conversion completes and the data registers are updated The ADC Conversion Complete Interrupt is executed if the ADIE bit and the I bit in SREG are set ADIF...

Page 126: ...in the unipolar mode as default but the bipolar mode can be selected by writing the BIN bit in the ADCSRB register In the unipolar mode only one sided conversions are supported and the voltage on the...

Page 127: ...ce that is cleared to a trigger source that is set will generate a positive edge on the trigger signal If ADEN in ADCSRA is set this will start a conversion Switching to Free Running mode ADTS 2 0 0 w...

Page 128: ...ystem uses a One wire bi directional interface to control the program flow execute AVR instructions in the CPU and to program the different non volatile memories 19 3 Physical Interface When the debug...

Page 129: ...erefore reduce the Falsh Data retention Devices used for debugging purposes should not be shipped to end customers 19 5 Limitations of debugWIRE The debugWIRE communication pin dW is physically locate...

Page 130: ...o the necessary changes and then write back the modified data If alter native 2 is used it is not possible to read the old data while loading since the page is already erased The temporary page buffer...

Page 131: ...in a page while the most significant bits are addressing the pages This is shown in Figure 20 1 Note that the Page Erase and Page Write operations are addressed independently Therefore it is of major...

Page 132: ...d within four clock cycles The CPU is halted during the entire Page Write operation Bit 1 PGERS Page Erase If this bit is written to one at the same time as SPMEN the next SPM instruction within four...

Page 133: ...LPM instruction is executed within three cycles after the RFLB and SPMEN bits are set in the SPMCSR the value of the Fuse Low byte FLB will be loaded in the destination register as shown below Refer...

Page 134: ...1 shows the typical pro gramming time for Flash accesses from the CPU 21 Memory Programming This section describes the different methods for Programming the ATtiny25 45 85 memories 21 1 Program And D...

Page 135: ...ming mode 1 debugWire is disabled 3 0 0 Further programming and verification of the Flash and EEPROM is disabled in High voltage and Serial Programming mode The Fuse bits are locked in both Serial and...

Page 136: ...of the Fuse bits is not affected by Chip Erase Note that the Fuse bits are locked if Lock bit1 LB1 is programmed Program the Fuse bits before programming the Lock bits 21 2 1 Latching of Fuses The fu...

Page 137: ...lash memory 3 0x002 0x0B indicates ATtiny85 device when 0x001 is 0x93 21 4 Calibration Byte Signature area of the ATtiny25 45 85 has one byte of calibration data for the internal RC Oscilla tor This b...

Page 138: ...programming operation in the Serial mode ONLY and there is no need to first execute the Chip Erase instruction The Chip Erase operation turns the content of every memory location in both the Program...

Page 139: ...the 6 MSB of the address If polling RDY BSY is not used the user must wait at least tWD_FLASH before issuing the next page See Table 21 9 Accessing the serial programming interface before the Flash w...

Page 140: ...ead Program Memory 0010 H000 0000 000a bbbb bbbb oooo oooo Read H high or low data o from Program memory at word address a b Load Program Memory Page 0100 H000 000x xxxx xxxb bbbb iiii iiii Write H hi...

Page 141: ...36 for details Write Fuse High bits 1010 1100 1010 1000 xxxx xxxx iiii iiii Set bits 0 to program 1 to unprogram See Table 21 4 on page 135 for details Write Extended Fuse Bits 1010 1100 1010 0100 xxx...

Page 142: ...5V Unless Otherwise Noted Symbol Parameter Min Typ Max Units 1 tCLCL Oscillator Frequency ATtiny25 45 85V 0 4 MHz tCLCL Oscillator Period ATtiny25 45 85V 250 ns 1 tCLCL Oscillator Frequency ATtiny25...

Page 143: ...igh voltage Serial Programming Characteristics TA 25 C 10 VCC 5 0V 10 Unless otherwise noted Symbol Parameter Min Typ Max Units tSHSL SCI PB3 Pulse Width High 125 ns tSLSH SCI PB3 Pulse Width Low 125...

Page 144: ...ations for Efficient Programming The loaded command and address are retained in the device during programming For efficient programming the following should be considered The command needs only be loa...

Page 145: ...ming cycle to finish 4 Repeat 2 through 3 until the entire Flash is programmed or until all data has been programmed 5 End Page Programming by Loading Command No Operation When writing or reading seri...

Page 146: ...ration 21 8 6 Reading the Flash The algorithm for reading the Flash memory is as follows refer to Table 21 16 1 Load Command Read Flash 2 Read Flash Low and High Bytes The contents at the selected add...

Page 147: ...er Flash Read mode Read Flash Low and High Bytes SDI SII SDO 0_bbbb_bbbb_00 0_0000_1100_00 x_xxxx_xxxx_xx 0_0000_000a_00 0_0001_1100_00 x_xxxx_xxxx_xx 0_0000_0000_00 0_0110_1000_00 x_xxxx_xxxx_xx 0_00...

Page 148: ...00_0000_00 0_0111_0100_00 x_xxxx_xxxx_xx 0_0000_0000_00 0_0111_1100_00 x_xxxx_xxxx_xx Wait after Instr 4 until SDO goes high Write F B 0 to program the Fuse bit Write Lock Bits SDI SII SDO 0_0010_0000...

Page 149: ...ng Characteristics TA 25 C 10 VCC 5 0V 10 Unless otherwise noted Symbol Parameter Min Typ Max Units tSHSL SCI PB3 Pulse Width High 110 ns tSLSH SCI PB3 Pulse Width Low 110 ns tIVSH SDI PB0 SII PB1 Val...

Page 150: ...Table 22 1 DC Characteristics TA 40 C to 125 C VCC 2 7V to 5 5V unless otherwise noted 1 Symbol Parameter Condition Min 2 Typ Max 3 Units VIL Input Low Voltage Except RESET and XTAL pins 0 5 0 3VCC V...

Page 151: ...C 5V 5 mA at VCC 3V under steady state conditions non transient the following must be observed 1 The sum of all IOH for all ports should not exceed 60 mA If IOH exceeds the test condition VOH may exce...

Page 152: ...vs VCC Table 22 2 External Clock Drive 1 PRELIMINARY Symbol Parameter VCC 2 7 5 5V VCC 4 5 5 5V Units Min Max Min Max 1 tCLCL Clock Frequency 0 8 0 16 MHz tCLCL Clock Period 100 50 ns tCHCX High Time...

Page 153: ...ock 1 MHz 3 LSB Single Ended Conversion VREF 4V VCC 4V ADC clock 200 kHz Noise Reduction Mode 1 5 LSB Single Ended Conversion VREF 4V VCC 4V ADC clock 1 MHz Noise Reduction Mode 2 5 LSB Integral Non l...

Page 154: ...uency loading of I O pins switching rate of I O pins code executed and ambient tempera ture The dominating factors are operating voltage and frequency The current drawn from capacitive loaded pins may...

Page 155: ...ctive Supply Current vs Frequency 1 20 MHz 5 5 V 5 0 V 4 5 V 4 0 V 3 3 V 2 7 V 0 000 0 005 0 010 0 015 0 020 0 025 0 030 0 035 0 040 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 8 0 9 1 Frequency MHz ACTIVE SUPPLY...

Page 156: ...vs VCC Internal RC Oscillator 1 MHz ACTIVE SUPPLY CURRENT vs VCC INTERNAL RC OSCILLATOR 128 KHz 125 C 85 C 25 C 40 C 0 0 05 0 1 0 15 0 2 0 25 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V I CC mA 125 C 85 C 25 C...

Page 157: ...y Current vs Frequency 0 1 1 0 MHz ACTIVE SUPPLY CURRENT vs V CC INTERNAL RC OSCILLATOR 8 MHz 0 1 2 3 4 5 6 7 8 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V I CC mA 125 C 85 C 25 C 40 C IDLE SUPPLY CURRENT vs LO...

Page 158: ...ternal RC Oscillator 128 kHz IDLE SUPPLY CURRENT vs FREQUENCY 1 20MHz 5 5 V 5 0 V 4 5 V 4 0 V 3 3 V 2 7 V 1 8 V 0 0 5 1 1 5 2 2 5 3 3 5 4 0 2 4 6 8 10 12 14 16 18 20 Frequency MHz Idle mA IDLE SUPPLY...

Page 159: ...s VCC Internal RC Oscillator 8 MHz 125 C 85 C 25 C 40 C IDLE SUPPLY CURRENT vs VCC INTERNAL RC OSCILLATOR 1 MHz 0 0 1 0 2 0 3 0 4 0 5 0 6 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V Idle mA IDLE SUPPLY CURRENT...

Page 160: ...6 4 for the USI 7 3 for the TIMER0 module and 21 4 for the ADC module Reading from Figure 23 9 we find that the idle current consumption is 0 25mA at VCC 3 0V and F 1MHz The total current consumption...

Page 161: ...23 12 Power Down Supply Current vs VCC Watchdog Timer Enabled POWER DOWN SUPPLY CURRENT vs VCC WATCHDOG TIMER DISABLED 125 C 85 C 25 C 40 C 0 0 5 1 1 5 2 2 5 3 3 5 4 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V...

Page 162: ...Pull Up Resistor Current vs Input Voltage VCC 2 7V I O PIN PULL UP RESISTOR CURRENT vs INPUT VOLTAGE Vcc 1 8V 125 C 85 C 25 C 40 C 0 10 20 30 40 50 60 0 0 2 0 4 0 6 0 8 1 1 2 1 4 1 6 1 8 2 VOP V I OP...

Page 163: ...s Reset Pin Voltage VCC 1 8V I O PIN PULL UP RESISTOR CURRENT vs INPUT VOLTAGE Vcc 5 0V 40 C 85 C 25 C 125 C 0 20 40 60 80 100 120 140 160 0 0 5 1 1 5 2 2 5 3 3 5 4 4 5 5 VOP V I OP uA RESET PULL UP R...

Page 164: ...sistor Current vs Reset Pin Voltage VCC 5 0V RESET PULL UP RESISTOR CURRENT vs RESET PIN VOLTAGE Vcc 2 7V 0 10 20 30 40 50 60 70 0 0 5 1 1 5 2 2 5 3 VRESET V I RE S E T uA 125 C 85 C 25 C 40 C 125 C 8...

Page 165: ...1 8V Figure 23 20 I O Pin Source Current vs Output Voltage VCC 3V I O PIN SINK CURRENT vs OUTPUT VOLTAGE VCC 1 8V 125 C 85 C 25 C 40 C 0 2 4 6 8 10 12 0 0 2 0 4 0 6 0 8 1 1 2 1 4 1 6 1 8 2 VOL V I OL...

Page 166: ...O Pin Sink Current vs Output Voltage VCC 1 8V I O PIN OUTPUT VOLTAGE vs SINK CURRENT Vcc 5 0V 125 85 25 40 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 5 10 15 20 25 IOL V V OL V I O PIN SOURCE CURRENT vs OUTPUT...

Page 167: ...re 23 24 I O Pin Sink Current vs Output Voltage VCC 5 0V I O PIN OUTPUT VOLTAGE vs SOURCE CURRENT Vcc 3V 125 85 25 40 0 0 5 1 1 5 2 2 5 3 3 5 0 5 10 15 20 25 IOH mA V OH V I O PIN OUTPUT VOLTAGE vs SO...

Page 168: ...6 I O Pin Input Threshold Voltage vs VCC VIL I O Pin Read As 0 I O PIN INPUT THRESHOLD VOLTAGE vs V CC VIH IO PIN READ AS 1 0 0 5 1 1 5 2 2 5 3 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V Thre s hold 125 C 85 C...

Page 169: ...old Voltage vs VCC VIH Reset Pin Read As 1 I O PIN INPUT HYSTERESIS 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 8 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V Thre s hold 125 C 85 C 25 C 40 C RESET INPUT THRESHOLD VOLTAGE v...

Page 170: ...set Input Pin Hysteresis vs VCC RESET INPUT THRESHOLD VOLTAGE vs V CC VIL IO PIN READ AS 0 0 0 5 1 5 2 2 5 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V Thre s hold 125 C 85 C 25 C 40 C 125 C 85 C 25 C 40 C RESET...

Page 171: ...BODLEVEL Is 2 7V BOD THRESHOLDS vs TEMPERATURE BODLEVEL 4 3V Rising Falling 4 4 05 4 1 4 15 4 2 4 25 4 3 4 35 4 4 50 40 30 20 10 0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 Temperature C Thre s h...

Page 172: ...uency vs VCC BOD THRESHOLDS vs TEMPERATURE BODLEVEL at 1 8V Rising Vcc Falling Vcc 1 6 1 65 1 7 1 75 1 8 1 85 1 9 50 40 30 20 10 0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 Temperature C Thre s h...

Page 173: ...CILLATOR FREQUENCY vs TEMPERATURE 5 5 V 4 0 V 3 6 V 2 7 V 1 8 V 0 1 0 102 0 104 0 106 0 108 0 11 0 112 0 114 0 116 0 118 40 30 20 10 0 10 20 30 40 50 60 70 80 90 100 110 120 Temperature F RC MHz CALIB...

Page 174: ...vs Osccal Value CALIBRATED 8MHz RC OSCILLATOR FREQUENCY vs OPERATING VOLTAGE 125 C 85 C 25 C 40 C 7 5 7 6 7 7 7 8 7 9 8 8 1 8 2 8 3 8 4 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V F RC MHz CALIBRATED 8MHz RC O...

Page 175: ...t vs VCC Figure 23 40 Analog Comparator Current vs VCC BROWNOUT DETECTOR CURRENT vs V CC 125 C 85 C 25 C 40 C 0 5 10 15 20 25 30 35 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V I CC uA ANALOG COMPARATOR CURRENT...

Page 176: ...Current through the Reset Pull up RESET SUPPLY CURRENT vs V CC 0 1 1 0 MHz EXCLUDING CURRENT THROUGH THE RESET PULLUP 5 5 V 5 0 V 4 5 V 4 0 V 3 3 V 2 7 V 1 8 V 0 0 02 0 04 0 06 0 08 0 1 0 12 0 14 0 0...

Page 177: ...ter Differential mode OFFSET vs VCC MINIMUM RESET PULSE WIDTH vs VCC 125 C 25 C 85 C 40 C 0 500 1000 1500 2000 2500 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V Puls e width ns Analog to Digital Converter OFFSET...

Page 178: ...l mode GAIN vs VCC Analog to Digital Converter OFFSET Single Ended Vcc 4V Vref 4V 0 0 5 1 1 5 2 2 5 40 30 20 10 0 10 20 30 40 50 60 70 80 90 100 110 120 Temperature LSB Analog to Digital Converter GAI...

Page 179: ...e DNL vs VCC Analog to Digital Converter GAIN Single Ended Vcc 4V Vref 4V 2 5 2 1 5 1 0 5 0 40 30 20 10 0 10 20 30 40 50 60 70 80 90 100 110 120 Temperature LSB Analog to Digital Converter Differentia...

Page 180: ...rter Differential Non Linearity DNL Single Ended Vcc 4V Vref 4V 0 47 0 48 0 49 0 5 0 51 0 52 0 53 0 54 0 55 0 56 0 57 40 30 20 10 0 10 20 30 40 50 60 70 80 90 100 110 120 Temperature LSB Analog to Dig...

Page 181: ...Analog to Digital Converter Single Endded mode INL vs VCC Analog to Digital Converter Integral Non Linearity INL Single Ended Vcc 4V Vref 4V 0 58 0 6 0 62 0 64 0 66 0 68 0 7 0 72 40 30 20 10 0 10 20 3...

Page 182: ...2 DWDR DWDR 7 0 page 129 0x21 WDTCR WDTIF WDTIE WDP3 WDCE WDE WDP2 WDP1 WDP0 page 42 0x20 PRR PRTIM1 PRTIM0 PRUSI PRADC page 33 0x1F EEARH EEAR8 page 16 0x1E EEARL EEAR7 EEAR6 EEAR5 EEAR4 EEAR3 EEAR2...

Page 183: ...age Notes 1 For compatibility with future devices reserved bits should be written to zero if accessed Reserved I O memory addresses should never be written 2 I O Registers within the address range 0x0...

Page 184: ...h Immediate Rd K Z N V C H 1 SBRC Rr b Skip if Bit in Register Cleared if Rr b 0 PC PC 2 or 3 None 1 2 3 SBRS Rr b Skip if Bit in Register is Set if Rr b 1 PC PC 2 or 3 None 1 2 3 SBIC P b Skip if Bit...

Page 185: ...d Indirect and Pre Dec Y Y 1 Rd Y None 2 LDD Rd Y q Load Indirect with Displacement Rd Y q None 2 LD Rd Z Load Indirect Rd Z None 2 LD Rd Z Load Indirect and Post Inc Rd Z Z Z 1 None 2 LD Rd Z Load In...

Page 186: ...3 ATtiny25 45 85 15ST ATtiny25 45 85 15ST1 ATtiny25 45 85 15SZ T5 Automotive 40 C to 85 C Automotive 40 C to 105 C Automotive 40 C to 125 C 2 7 5 5V 8 16 3 ATtiny25 45 85 15MT ATtiny25 45 85 15MT1 AT...

Page 187: ...187 7598H AVR 07 09 ATtiny25 45 85 27 Packaging Information 27 1 T5...

Page 188: ...188 7598H AVR 07 09 ATtiny25 45 85 27 2 PC...

Page 189: ...598D 02 07 1 Clarification of Power On Reset Specifications table Table 8 1 on page 37 2 Errata list updated 3 Added QFN packages 28 6 Revision 7598C 09 06 1 Correction of package codification and dra...

Page 190: ...section refers to the revision of the ATtiny25 45 85 device 29 1 ATtiny25 Revision E 1 No known errata Flash security improvements 29 2 ATtiny45 Revision G 1 No known errata Flash security improvement...

Page 191: ...4 7 Instruction Execution Timing 11 4 8 Reset and Interrupt Handling 11 5 AVR ATtiny25 45 85 Memories 13 5 1 In System Re programmable Flash Program Memory 13 5 2 SRAM Data Memory 14 5 3 EEPROM Data M...

Page 192: ...atus Register MCUSR 40 8 8 Internal Voltage Reference 40 8 9 Watchdog Timer 41 8 10 Timed Sequences for Changing the Configuration of the Watchdog Timer 44 9 Interrupts 45 9 1 Interrupt Vectors in ATt...

Page 193: ...DT1A 95 15 3 Timer Counter1 Dead Time B DT1B 95 16 Universal Serial Interface USI 96 16 1 Overview 96 16 2 Functional Descriptions 97 16 3 Alternative USI Usage 103 16 4 USI Register Descriptions 103...

Page 194: ...e 137 21 5 Page Size 137 21 6 Serial Downloading 138 21 7 High voltage Serial Programming 142 21 8 High voltage Serial Programming Algorithm Sequence 144 21 9 High voltage Serial Programming Character...

Page 195: ...g Information 187 27 1 T5 187 27 2 PC 188 28 Document Revision History 189 28 1 Revision 7598H 07 09 189 28 2 Revision 7598G 03 08 189 28 3 Revision 7598F 11 07 189 28 4 Revision 7598E 03 07 189 28 5...

Page 196: ...R STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTY OF MERCHANTABILITY FITNESS FOR A PARTICULAR PURPOSE OR NON INFRINGEMENT IN NO EVENT SHALL ATMEL BE LIABL...

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