33
7598H–AVR–07/09
ATtiny25/45/85
Note that if a level triggered interrupt is used for wake-up from Power-down mode, the changed
level must be held for some time to wake up the MCU. Refer to
“External Interrupts” on page 58
for details
.
.
Note:
1. For INT0, only level interrupt.
7.5
Limitations
BOD disable functionality has been implemented in the following devices, only:
• ATtiny25, revision D, and newer
• ATtiny45, revision D, and newer
• ATtiny85, revision C, and newer
7.6
Power Reduction Register
The Power Reduction Register, PRR, provides a method to stop the clock to individualperipher-
als to reduce power consumption. The current state of the peripheral is frozenand the I/O
registers can not be read or written. Resources used by the peripheral when stopping the clock
will remain occupied, hence the peripheral should in most cases be disabled before stopping the
clock. Waking up a module, which is done by clearing the bit in PRR, puts the module in the
same state as before shutdown.
Module shutdown can be used in Idle mode and Active mode to significantly reduce the overall
power consumption. In all other sleep modes, the clock is already stopped.
• Bits 7, 6, 5, 4- Res: Reserved Bits
These bits are reserved bits in the ATtiny25/45/85 and will always read as zero.
• Bit 3- PRTIM1: Power Reduction Timer/Counter1
Writing a logic one to this bit shuts down the Timer/Counter1 module. When the Timer/Counter1
is enabled, operation will continue like before the shutdown.
Table 7-2.
Active Clock Domains and Wake-up Sources in the Different Sleep Modes
Active Clock Domains
Oscillators
Wake-up Sources
Sleep Mode
clk
CPU
cl
k
F
L
ASH
clk
IO
cl
k
ADC
cl
k
PCK
Mai
n
Cloc
k
Source Enab
led
INT0 and
Pin
C
hang
e
SPM/
EEPR
OM
Re
ady
USI Star
t Cond
ition
ADC
Ot
her I
/O
W
a
tchdog
Interr
upt
Idle
X
X
X
X
X
X
X
X
X
X
ADC Noise
Reduction
X
X
X
X
X
X
X
Power-down
X
X
X
Bit
7
6
5
4
3
2
1
0
–
-
-
-
PRTIM1
PRTIM0
PRUSI
PRADC
PRR
Read/Write
R
R
R
R
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
