Evaluation Kit AT697F V3.0 [APPLICATION NOTE]
20
2.10
Clock management
2.10.1 Clock overview
Figure 2-14. AT697F Clock distribution
Figure 2-15. Development kit clock management
SPP Connector
RS232 serial link
connector
Clock
generator
PLL configuration
AT697F
Clock
configuration
CLK EXT 1
connector
UART Clock
configuration
CLK EXT 2
connector
Legend:
Configuration switch
Connector
Clock
interface
PCI
interface
SKEW 1 configuration
SKEW 0 configuration
UART
interface
PIO
interface
UART Control Reg.
UACn
PB Enter
25 MHz
33 MHz