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Atmel AT697F User Manual Download Page 14

 

 

Evaluation Kit AT697F V3.0 [APPLICATION NOTE] 

14 

 

Table 2-2 PROM code sizes 

 

ROM bus width 

EDAC 

Code size 

8 bits 

Disabled 

8 Mbits x1 

– 8 Mbits available 

8 bits (add a 5

th

 bit for EDAC) 

Enabled 

8 Mbits x1 

– 6.55 Mbits available 

32 bits 

Disabled 

8 Mbits x2 

– 16 Mbits available 

40 bits (32 bits data + 8 bits EDAC) 

Enabled 

8 Mbits x3 

– 16 Mbits available 

 

IMPORTANT: until now, PROM8 is not recognized by GRMON. 

 

The AT697 PROM bus width is configured at reset time according to PIO[1:0] value. Under reset the processor samples 

PIO[1:0] and reports its value to the memory configuration register. 

 

2.6.2.2  PROM40 Configuration (SW37.7 is OFF) 

 

The 40-bit boot PROM is based on three M29W800D Flash memories (U19, U20 and U21). These chips are directly 

soldered on the board. PROM 40 is implemented on the bottom side of the board as shows the following picture: 

 

 

Figure 2-8. PROM40 implementation 

 

 

In order to use the 40-bit mode, the following configuration shall be respected: SW37.7 is OFF. 

 

2.6.2.3  PROM8 Configuration (SW37.7 is ON) 

 

The 8-bit boot PROM is based on three M29W800D Flash memories (U22). The chip is directly soldered on the board. 

PROM8 is implemented on the bottom side of the board close to the PROM40. 

 

IMPORTANT:

 when EDAC is activated with PROM8, memory available is less than without EDAC. 

Summary of Contents for AT697F

Page 1: ...ource connection RS232 hardware connector dedicated to the Debug Support Unit DSU RS232 hardware connector dedicated to a universal UART PCI interface Host Satellite capability User defined push buttons User defined LEDs Expansion connector 10 pin JTAG interface connector Description The AT697F Evaluation Kit is a development system for the ATMEL AT697F 32 bit SPARC V8 processor based on LEON2 fau...

Page 2: ...1 Board press buttons 17 2 7 2 Board LEDs 17 2 7 3 Board display 18 2 8 UART interface 18 2 8 1 Serial link 1 18 2 8 2 Serial link 2 19 2 9 PCI interface 19 2 10 Clock management 20 2 10 1 Clock overview 20 2 10 2 Internal clocks 21 2 10 3 External clocks 21 2 10 4 Processor clock configuration 21 2 11 Evaluation Kit Reset 22 2 11 1 Hardware reset 22 2 11 2 Alternate reset 22 2 11 3 Supply voltage...

Page 3: ...ing software development package 32 3 5 Hardware setup 33 3 5 1 Default switches configuration 33 3 5 2 Power supply setup 33 3 5 3 Serial communication link 33 3 5 4 GRMON 33 3 6 Run your first application 34 4 Appendix B Schematics 38 5 Revision History 38 ...

Page 4: ...ping easly applications running on an AT697F processor This guide focuses on the description of the AT697F evlaluation kit 1 2 Deliverables The AT697F evaluation kit package contains the following items 1x AT697F Evaluation kit Rev 3 0 1x AT697F processor in MQFP256 package 1x Power supply cable with 2 1mm Jack connector 2x RS232 cables 1 CD Rom ...

Page 5: ...clock generator 100MHz with PLL 33MHz PCI Connector 1x RS232 1x Clock Configuration Manager SPP 2x SMB Clock input 1x JTAG 1x RS232 Debug Interface 2x Expansion Connectors 1x Compact PCI 1x SMB Analog input 2x Expansion connector Memory 8 Mbits flash 32 bits wide 40 bits capability 8 Mbits flash 8 bits wide 16 Mbits SRAM 32 bits wide 40 bits capability 256 Mbits SDRAM 32 bits wide 40 bits capabili...

Page 6: ...G Connector Clock PLL configuration PCI AMBA Controller AMBA bridge PCI AMBA bridge DSUACT LED DSUBRE Button PCI interface LCD Display Current measurement Flash 8 bits AIN Connector Potentiometer Temperature Sensor ADC RS232 Reset control Reset Reset configuration Regulators Alternate reset Flash conf EDAC configuration Clock configuration CLK EXT 1 connector Reset button UART Clock configuration ...

Page 7: ...w 1V8 direct power 3V3 direct power 5V direct power EXT power 8 12V 1V8 source selection 3V3 source selection 5V source selection Power Supply CPCI Connector HMI Buttons HMI LEDs Configuration switches LCD 240x320 SRAM SDRAM Buffers Clocks generator Expansion connector Expansion connector DSU interface ...

Page 8: ...guration switches Table 2 1 Initial configuration state Name Initial state Function SW37 1 OFF Actives EDAC SW37 2 ON Actives the Bypass thus disable the PLL SW37 3 OFF SKEW 0 configuration SW37 4 OFF SKEW 1 configuration SW37 5 OFF Connect the processor watchdog to the RESET device SW37 6 OFF Select the processor clock SW37 7 OFF This switch will select the PROM width SW37 8 OFF Select PIO3 signa...

Page 9: ...ecommended that the power supply is current limited in order to prevent damage to the board or power supply in case of over current Evaluation board can be powered through different ways Figure 2 5 Power supply diagram When PCI is used 3V3 regulator and 5V regulator are automatically shut down to avoid conflict with CPCI power supplies Important when the board is powered from the CPCI connector sw...

Page 10: ...CATION NOTE 10 2 5 Processor 2 5 1 Processor Package On the evaluation kit the AT697 32 bit SPARC processor is embedded The processor package is the MQFP 256 space qualified package Figure 2 6 MQFP 256 package 2 5 2 Processor Pin out ...

Page 11: ...Evaluation Kit AT697F V3 0 APPLICATION NOTE 11 ...

Page 12: ...Evaluation Kit AT697F V3 0 APPLICATION NOTE 12 ...

Page 13: ...0 bits SDRAM 40 bits Buffer Flash 8 bits AT697F Logic to configure buffer operation Legend Fast memory Slow memory Flash configuration Switch 2 6 2 PROM or Flash 2 6 2 1 PROM Overview The AT697F is able to work with two bus widths 8 bits or 32 bits In both cases the processor can use the EDAC mode If EDAC is enabled on the PROM 40 the processor needs 8 more bits The evaluation kit is delivered wit...

Page 14: ...ue to the memory configuration register 2 6 2 2 PROM40 Configuration SW37 7 is OFF The 40 bit boot PROM is based on three M29W800D Flash memories U19 U20 and U21 These chips are directly soldered on the board PROM 40 is implemented on the bottom side of the board as shows the following picture Figure 2 8 PROM40 implementation In order to use the 40 bit mode the following configuration shall be res...

Page 15: ...t allows the user to work with SRAM and SDRAM 2 6 3 1 SRAM Configuration The evaluation kit implements one bank of SRAM which starts at memory address 0x40000000 There are 2 components for this function 1x SRAM 32 bits for the data code AT68166F YS18 E U35 1x SRAM 8 bits for the checkbit EDAC protection AT60142H DS15M E U36 This provides an access to 16MBits of SRAM data code Because of an inversi...

Page 16: ...s 0x60000000 There are 2 components for this function 2x SDRAM 16 bits for the data code MT48LC16M16A2P 6A U25 U26 1x SDRAM 16 bits only 8 bits are used for the checkbit EDAC protection MT48LC16M16A2P 6A U27 This provides an access to 256MBits of SDRAM data code Figure 2 10 SDRAM implementation Bottom side Top side 2 1 SDRAM for data 2 SDRAM for EDAC 1 ...

Page 17: ... Press button implantation Table 2 3 Press buttons mapping Name Function Processor connexion HMI_PB1 Press button left PIO 13 HMI_PB2 Press button right PIO 12 HMI_PB3 Press button up PIO 10 HMI_PB4 Press button down PIO 11 HMI_PB5 1 Press button enter 1 PIO 3 1 To use this function SW37 8 must be OFF 2 7 2 Board LEDs LEDs are driven by a NPN transistor A hight level on a PIO put the LED on Figure...

Page 18: ...5 HMI_LCD_NWR_SCL Display serial clock PIO 6 HMI_LCD_CS Display chip select PIO 9 2 8 UART interface The AT697 evaluation board includes all the required hardware to manage a RS232 communication Hardware flow control CTS RTS are not implemented on this Evaluation Kit 2 8 1 Serial link 1 Serial link 1 is available on the board through the connector UART 1 accessible on the front panel see Figure 2 ...

Page 19: ...driver like MAX3232 has to be implemented to adapt voltage 2 9 PCI interface The AT697 evaluation board implements a PCI interface capable to manage host and satellite configuration The PCI interface has been designed to be integrated in compact PCI back plane Universal keying is implemented The board form factor fits with the 6U standard The HOST SATELLITE mode is automatically configured through...

Page 20: ... management SPP Connector RS232 serial link connector Clock generator PLL configuration AT697F Clock configuration CLK EXT 1 connector UART Clock configuration CLK EXT 2 connector Legend Configuration switch Connector Clock interface PCI interface SKEW 1 configuration SKEW 0 configuration UART interface PIO interface UART Control Reg UACn PB Enter 25 MHz 33 MHz ...

Page 21: ...T clock used if SW37 8 ON 2 10 4 Processor clock configuration Configuration switches SW37 allow the user to manage processor clock configuration Table 2 7 Clock configuration Name Switch number Function Processor pin BYPASS 2 OFF PLL enable master clock frequency is equal to 4x CLK frequency ON PLL disabled master clock frequency is equal to CLK frequency 176 N15 SKEW 0 3 OFF SKEW0 disabled ON SK...

Page 22: ...pushing the embedded RESET push button implanted on the front panel see Figure 2 3 Front panel overview A pressure on the RESET button leads to the reset of both the processor core and the PCI interface 2 11 2 Alternate reset An alternate reset is available on the expansion connector Please refer to the Expansion Connectors section 2 15 for detailed information on expansion connector assignments 2...

Page 23: ...nnect WDOG pin to reset module ON disconnect WDOG pin to reset module 168 M17 2 12 Debug Support Unit Debug Support Unit DSU includes several parts A DSU connector to communicate A DSUACT LED to indicate if the processor is in debug mode A DSUBRE Press button to allow the user to put the processor in debug mode The AT697 Debug Support Unit is based on a RS232 serial link connected to a host platfo...

Page 24: ... table gives the pinout of the JTAG connector Table 2 9 JTAG pinout J8 JTAG connector pin number Signal name 1 JTAG TCK 2 GND 3 JTAG TDO 4 VCC3V3 5 JTAG TMS 6 JTAG TRST 7 VCC3V3 8 N C 9 VCC3V3 TDI 10 GND 2 14 Test Points 2 14 1 Current measurement test points Current measurement test points are arranged according to the following drawing 2 54mm 2 54mm 2 54mm GND GND R shunt 0 01R A B C Figure 2 18...

Page 25: ...E 25 2 14 2 Clocks test points TP_DEVICE_1V8 TP_ DEVICE _3V3 TP_BOARD _1V8 TP_BOARD_3V3 TP_I_1V8 TP_BOARD_5V TP_I_1V8_PLL SDCLK CLK ext 1 CLK ext 2 Processor clock input 25 MHz 33 MHz Figure 2 19 Power test points Figure 2 20 Clock test points ...

Page 26: ...Evaluation Kit AT697F V3 0 APPLICATION NOTE 26 2 14 3 System and CPCI test points Processor error PCI reset PCI clock BEXC Board reset Figure 2 21 System and CPCI test points ...

Page 27: ...79 PCI_AD20 80 PCI_RST 139 HMI_LCD_D2 140 N C 190 GND 21 N C 22 N C 81 PCI_AD19 82 PCI_SYSEN 141 HMI_LCD_D3 142 N C 191 GND 23 N C 24 N C 83 PCI_AD18 84 PCI_FRAME 143 HMI_LCD_D4 144 N C 192 GND 25 N C 26 N C 85 PCI_AD17 86 PCI_IRDY 145 HMI_LCD_D5 146 N C 193 N C 27 N C 28 N C 87 PCI_AD16 88 PCI_TRDY 147 HMI_LCD_D6 148 N C 194 N C 29 N C 30 N C 89 PCI_AD15 90 PCI_IDSEL 149 HMI_LCD_D7 150 N C 31 N C...

Page 28: ...3V3 24 TCK 83 RAMOE0 84 PIO4 143 A11 144 D11 192 GND 25 BOARD_3V3 26 TRST 85 RAMOE1 86 PIO3 145 A12 146 D12 193 N C 27 BOARD_5V 28 DSUEN 87 RAMOE2 88 PIO2 147 A13 148 D13 194 N C 29 BOARD_5V 30 DSURX 89 RAMOE3 90 PIO1 149 A14 150 D14 31 BOARD_5V 32 DSUTX 91 RAMOE4 92 PIO0 151 A15 152 D15 33 BOARD_5V 34 DSUACT 93 RWE0 94 HMI_LED0 153 A16 154 D16 35 BOARD_5V 36 DSUBRE 95 RWE1 96 HMI_LED1 155 A17 156...

Page 29: ...Evaluation Kit AT697F V3 0 APPLICATION NOTE 29 2 16 Mechanical drawing Figure 2 22 PCB mechanical drawing 233 35 160 mm 106 7 5 97 5 6 ...

Page 30: ...requiring a global view of the board and requiring additional measurement constraints over the board Such file can be read and analyzed with Allegro Free Physical Viewer a free tool from Cadence 2 17 Board History Table 2 12 Board history Version Comments AT697F Evaluation Kit V3 0 1 First release AT697F Evaluation Kit V3 0 2 Change U23 to a TPS386040RGP Add manual fixes to have access to SRAM8 fr...

Page 31: ...section describes the content of the AT697 development environment Hardware AT697 Evaluation Board AT697F Processor One Power supply cable with 2 1mm Jack connector Two RS232 cables Software Gaisler Research RCC BCC software packages GRMON1 Professional version under Gaisler Research License Notes 1 only for Development kit Documentation AT697 Evaluation Kit User Manual AT697 datasheet and erratas...

Page 32: ...ows platforms the Cygwin Unix emulation layer needs to be installed Cygwin 1 1 7 or higher is recommended on this platform Under Linux platform Linux 2 4 x with glibc 2 3 or higher is recommended The minimum hardware requirements are Pentium 1 Processor 128 MB RAM 100 MB Available Hard Disk Space 115200 Baud RS 232 Port COM port 3 4 Installing software development package Here is a summary of the ...

Page 33: ... with a voltage comprised between 8V and 12V Power supplies switches should be on Reg position to use onboard regulators 3 5 3 Serial communication link For application download and debug you shall connect the serial interface of the board to the host monitor With the AT697 Development kit the GRmon debug monitor from Gaisler Research is available 3 5 4 GRMON GRMON requires a single RS232 communic...

Page 34: ...piling to ROM In addition you can create the ROM boot strap using sparc elf mkprom application o rom_application Step 2 Hardware configuration Connect the DSU connector of the Evaluation kit to the computer through a serial cable In your Operating System hardware properties find your Port COM Number for example COM1 Use the default configuration switches table 2 1 to use internal clock without PLL...

Page 35: ...WS grmon leon2 uart COM1 baud 115200 romws 15 ramws 3 under LINUX grmon leon2 uart dev ttyS0 baud 115200 romws 15 ramws 3 where the uart and baud flags are to be set according to your communication interface configuration and the romws and ramws flags are to be tuned with respect to the AT697F internal clock frequency Other options can be added to the command line Please refer to the GRmon user ma...

Page 36: ...files hex are Use cd your_directory command to jump to the directory Use cd to jump to the parent directory Step 5A load to RAM The executable can be loaded to RAM applying the following command load application Step 5B load to ROM The ROM boot strap can be loaded to the on board flash applying the following commands flash enable flash erase all flash load rom_application ...

Page 37: ... 0 APPLICATION NOTE 37 Step 5A execute code from RAM To execute the loaded program use run command Step 5B execute code from ROM There are two ways to execute the code Use go 0 command under GRMON Or restart the Evaluation Kit ...

Page 38: ...fer to the file in pdf format contained in the CD ROM to see the Evaluation Kit schematic 5 Revision History Doc Rev Date Comments 7540F 02 2013 Initial document release 7540G 12 2014 Add fixes for SRAM8 access problem 7540H 10 2015 Change comments when using CPCI rack power supply ...

Page 39: ...products EXCEPT AS SET FORTH IN THE ATMEL TERMS AND CONDITIONS OF SALES LOCATED ON THE ATMEL WEBSITE ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTY OF MERCHANTABILITY FITNESS FOR A PARTICULAR PURPOSE OR NON INFRINGEMENT IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT INDIRECT ...

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