Evaluation Kit AT697F V3.0 [APPLICATION NOTE]
21
2.10.2 Internal clocks
The Development kit embeds 2 internal clocks provided by one integrated circuit U4:
The main processor clock (25 MHz), used if SW37.6 = OFF.
The PCI clock (33 MHz)
2.10.3 External clocks
Two SMB male connectors are accessible from the front panel of the Evaluation Kit (see Figure 2-3. Front panel
Clock EXT IN 1: alternate processor clock, used if SW37.6 = ON.
Clock EXT IN 2: alternate UART clock, used if SW37.8 = ON.
2.10.4 Processor clock configuration
Configuration switches SW37 allow the user to manage processor clock configuration.
Table 2-7 Clock configuration
Name
Switch number
Function
Processor pin
BYPASS
2
OFF: PLL enable, master clock frequency is equal
to 4x CLK frequency.
ON: PLL disabled, master clock frequency is
equal to CLK frequency.
176 / N15
SKEW 0
3
OFF: SKEW0 disabled
ON: SKEW0 enable
175 / M19
SKEW 1
4
OFF: SKEW1 disabled
ON: SKEW1 enable
174 / M14
CLK
6
OFF: processor use on-board 25MHz clock
ON: processor use Clock EXT IN 1
180 / P15
UART CLK
8
OFF: PIO3 is connected to Press Button ENTER
ON: PIO3 is connected to Clock EXT IN 2
63 / F4