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MDR User Guide
101
Signal Termination
Signal DPIO-FI DPIO-FO DPIO-EI DPIO-EO DPIO-DI/LI
DPIO-DO/LO
SUSPEND*
330
Ω
pull down
220
Ω
pull up
330
Ω
pull down
220
Ω
pull up
390
Ω
to GND on
both + and - wires
110
Ω
across
+ and – wires
110
Ω
across
+ and – wires
DIR*
330
Ω
pull down
220
Ω
pull up
330
Ω
pull down
220
Ω
pull up
NA NA NA
NRDY*
330
Ω
pull down
220
Ω
pull up
330
Ω
pull down
220
Ω
pull up
NA NA
110
Ω
across
+ and – wires
STROB
330
Ω
pull down
220
Ω
pull up
330
Ω
pull down
220
Ω
pull up
110
Ω
across
+ and – wires
390
Ω
to GND on
both + and - wires
110
Ω
across
+ and – wires
PSTROB
PSTROB*
110
Ω
across
+ and – wires
390
Ω
to GND on
both + and - wires
NA NA NA
DATA 27
Ω
series
110
Ω
across
+ and – wires
390
Ω
to GND on
both + and - wires
110
Ω
across
+ and – wires
DVALID 27
Ω
series
110
Ω
across
+ and – wires
390
Ω
to GND on
both + and - wires
110
Ω
across
+ and – wires
SYNC 27
Ω
series
110
Ω
across
+ and – wires
390
Ω
to GND on
both + and - wires
110
Ω
across
+ and – wires
PIO2:1
27
Ω
series¤
27
Ω
series
110
Ω
across
+ and – wires
390
Ω
to GND on
both + and - wires
110
Ω
across
+ and – wires
110
Ω
across
+ and – wires
RES3
27
Ω
series¤
27
Ω
series
NA NA
110
Ω
across
+ and – wires
RES2:1
27
Ω
series¤
27
Ω
series
NA NA NA
NA
¤
when connected
FPDP Options
The FPDP standard defines a number of signals, which may be used differently in
different modes of operation. This section describes their usage in the MDR.
Clocking
Input module (DPIO-FI)
Two separate clocks are provided on the FPDP. STROB is a single-ended clock
conforming to TTL levels, while PSTROB and /PSTROB is a differential Positive
Emitter-Coupled Logic version of the same clock. Either of these signals may be used on
a FPDP input module. However, the PSTROB, /PSTROB signal pair is preferable,
especially at higher clocking frequencies and when driving longer lines, since the noise
margin is improved over the TTL clock. A control register bit on the DPIO selects
between the two clocks. This choice between these two sorts of signals will be available
from the version 1.2 of the MDR.
Output module (DPIO-FO)
A replaceable oscillator is used to generate clocks when operating as data source. The
oscillator frequency can be used directly or be divided by 2, 4, or 8 by means of control
register bits. This can be setup with the item called
OutputFreqDivisor
in the
DpioInfo
section of the
mdr.ini
file.
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