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Artesyn COMX-P40x0 ENP2, Manual

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COMX-P40x0 ENP2

Installation and Use

P/N: 6806800R95B
August 2014

Summary of Contents for COMX-P40x0 ENP2

Page 1: ...COMX P40x0 ENP2 Installation and Use P N 6806800R95B August 2014...

Page 2: ...anges from time to time in the content hereof without obligation of Artesyn to notify any person of such revision or changes Electronic versions of this material may be read online downloaded for pers...

Page 3: ...llation 27 2 1 Environmental and Power Requirements 27 2 1 1 Environmental Requirements 27 2 2 Unpacking and Inspecting the Enclosure 29 2 3 Installing and Removing the Module on the Carrier Board 30...

Page 4: ...0 4 12 LAN 71 4 12 1 MDIO 71 4 13 PHY 73 4 14 UART Interface 73 4 15 Real Time Clock 73 4 16 Watchdog Timer 73 4 17 USB 73 4 18 I2C Interface 74 4 18 1 I2C Device Thermal Sensor 76 4 18 2 I2C Device E...

Page 5: ...ts on NOR Flash 88 7 6 5 Address Variables for the Boot Components in RAM 89 7 6 6 Device Variables 89 7 6 7 HWCONFIG Variable 89 7 6 8 Bootargs Variable 90 7 6 9 Bootup Variables 90 7 7 Checking the...

Page 6: ...7 22 1 Pre Deployment Steps 117 7 22 2 Deploying BSP Images on NOR FLASH 119 7 23 Boot 119 7 23 1 RAMboot 120 7 23 2 NORboot 120 7 23 3 NANDboot 121 7 23 4 NFSboot 122 7 23 5 USBFATboot and USBEXT2boo...

Page 7: ...s 63 Table 4 4 Memory Map 67 Table 4 5 GPIO 68 Table 4 6 GPIO 70 Table 4 7 SD or Micro SD card on the Carrier 70 Table 4 8 I2C Interface 75 Table 5 1 Configuration of the frequency of SERDES reference...

Page 8: ...COMX P40x0 ENP2 Installation and Use 6806800R95B 8 List of Tables...

Page 9: ...al Number Location 25 Figure 2 1 Mounting Module on Carrier Board 32 Figure 2 2 Heat sink installation 33 Figure 4 1 COMX P40x0 ENP2 Block Diagram 58 Figure 4 2 Distribution of Local Bus on P40x0 60 F...

Page 10: ...COMX P40x0 ENP2 Installation and Use 6806800R95B 10 List of Figures...

Page 11: ...and the setup utility used to configure the module Power Domains describes the power supply system for the module BSP describes how to build the Basic Support Package BSP and deploy the built images o...

Page 12: ...erface Express next generation high speed Serialized I O bus PHY Ethernet controller physical layer device Pin out Type AreferencetooneoffiveCOMExpressTMdefinitionsforwhatsignals appear on the COM Exp...

Page 13: ...enoutputandcoderelatedelements or commands in body text Courier Bold Used to characterize user input and to separate it from system output Reference Used for references and for table and figure descri...

Page 14: ...which if not avoided could result in death or serious injury Indicates a hazardous situation which if not avoided may result in minor or moderate injury Indicates a property damage message No danger...

Page 15: ...table via carrier Demo runtime Linux Operating System and filesystem s pre installed in NOR NAND Flash Dual channel on board DDR3 with ECC COMX P40x0 2G boards have 1GB per channel for a total of 2GB...

Page 16: ...is designed to meet the following standards Due to P4080 errata GEN A009 Aurora ports are disabled by default in RCW and must be re enabled for debug For assistance contact Artesyn representative Tab...

Page 17: ...EN 55024 EMC Requirements on system level ETSI EN 300 019 Series Environmental Requirement Directive 2011 65 EU Directive on the restriction of the use of certain hazardous substances in electrical a...

Page 18: ...EC 2006 95 EC 2011 65 EU and their amending directives Product COMX P40x0 ENP2 Express Form Factor Processor Pluggable Mez zanine Module For Extended Temperature and rugged Environments Model Name Nu...

Page 19: ...f COMX P4080 ENP2 and COMX P4040 ENP2 boards Figure 1 2 COMX P40X0 ENP2 Top View D6 1 8V power ok D3 system asleep D4 3 3V power ok D5 2 5V power ok D9 Platform Power OK D13 CORE power ok Debug led D1...

Page 20: ...Introduction COMX P40x0 ENP2 Installation and Use 6806800R95B 20 Figure 1 3 COMX P40X0 ENP2 Bottom View PIN B1 PIN A1 PIN B1 PIN A1 COME CD J3 COME AB J2...

Page 21: ...0x0 ENP2 Installation and Use 6806800R95B 21 1 3 1 COMX P4080 ENP2 The following figure illustrates the top and side views of the COMX P4080 ENP2 board Figure 1 4 COMX P4080 ENP2 Mechanical Dimensions...

Page 22: ...on COMX P40x0 ENP2 Installation and Use 6806800R95B 22 Table 1 2 COMX P4080 ENP2 PCB Dimensions Characteristic Value Length 125 mm Width 95 mm PCB Thickness 2 mm Mounting height top side component sid...

Page 23: ...0x0 ENP2 Installation and Use 6806800R95B 23 1 3 2 COMX P4040 ENP2 The following figure illustrates the top and side views of the COMX P4040 ENP2 board Figure 1 5 COMX P4040 ENP2 Mechanical Dimensions...

Page 24: ...top side component side 1 9 65 mm Table 1 4 Ordering Information Order Number Description COMX P4080 2G ENP2 QorIQ P4080 with 2GB DDR3 0 Gigabit Ethernet 5 USB ports COM Express Basic size COMX P4080...

Page 25: ...The following figure shows the location of serial number on COMX P4080 ENP2 board 1 5 2 COMX P4040 ENP2 The following figure shows the location of serial number on COMX P4040 ENP2 board Figure 1 6 CO...

Page 26: ...Introduction COMX P40x0 ENP2 Installation and Use 6806800R95B 26...

Page 27: ...12 CFM system airflow volume at 71o C is needed for the heat sink to keep sufficient cooling to the module Contact your Artesyn sales representative for detailed thermal information Operating temperat...

Page 28: ...erature Spots Component Identifier Heat Dissipation Power W Maximum Allowable Temperature C CPU P4080 20 5 CPU 105 Tj CPU P4040 16 8 CPU 105 Tj Memory SDRAM 3 95 Tc GbE Transceiver BCM5482 0 86 125 Tj...

Page 29: ...urrent Drawn State 12v VCC_RTC Idle 2 81A 100 uA Full Loading Linux 2 91A 100 uA Table 2 4 COMX P4080 4G E ENP2 Volts Amps Power 12 2 6 31 2 Total Power dissipation W 31 2 Damage of Circuits Electrost...

Page 30: ...t sink is assembled to the module before the procedure below Installing the COM module on the carrier board 1 Line up the board to board connector of the module assembly with the board to board connec...

Page 31: ...corresponding to the module standoffs 4 Use the screws to fasten the module to the carrier board Removing the module from the carrier board 1 From the back side of the carrier locate the five screws...

Page 32: ...6806800R95B 32 The figure below illustrates the screw holes for mounting the module on carrier board Figure 2 1 Mounting Module on Carrier Board This installation removal procedure is only for referen...

Page 33: ...reparation and Installation COMX P40x0 ENP2 Installation and Use 6806800R95B 33 Heat sink Installation The following figures illustrate the heat sink installation on the module Figure 2 2 Heat sink in...

Page 34: ...Hardware Preparation and Installation COMX P40x0 ENP2 Installation and Use 6806800R95B 34 Figure 2 2 Heat sink installation continued...

Page 35: ...owing table lists the pin out of the COP Common On Chip Processor header for modules with the P4080 CPU Table 3 1 P4080 COP Header Pin out Pin Signal Name 1 GND 2 cpu_ckstp_out_n 3 key for p4040 cop n...

Page 36: ...he pin out of the COP header for modules with the P4040 CPU Table 3 2 P4040 COP Header Pin out Pin Signal Name 1 cpujtag_tdo 2 empty 10k pullup 3 cpujtag_tdi 4 TRST 5 NC RUNSTOP 6 VDDSENSE 3 3V 7 TCK...

Page 37: ...for the P40x0 COMX modules Table 3 3 Module LED Status LED Status D17 Thermal issue D18 D19 Debug LED 1 2 D3 System asleep D7 DDR3 power OK D4 3 3V power OK D5 2 5V power OK D6 1 8V power OK D13 CORE...

Page 38: ...t out from comx J2 AB1 A9 LAN1_MDI_N 1 bidir J2 AB1 A10 LAN1_MDI_P 1 bidir J2 AB1 A11 GND J2 AB1 A12 LAN1_MDI_N 0 bidir J2 AB1 A13 LAN1_MDI_P 0 bidir J2 AB1 A14 V1P8_CTRL out out from comx 1 8v power...

Page 39: ...J2 AB1 A36 N C J2 AB1 A37 N C J2 AB1 A38 N C J2 AB1 A39 N C J2 AB1 A40 N C J2 AB1 A41 GND J2 AB1 A42 USB2_N bidir J2 AB1 A43 USB2_P bidir J2 AB1 A44 USB_OC_2_3_N in J2 AB1 A45 USB0_N bidir J2 AB1 A46...

Page 40: ...TIVITY_N out lan1 activity J2 AB1 B3 TSEC_1588_CLK_OUT out J2 AB1 B4 TSEC_1588_PULSE_OUT1 out J2 AB1 B5 TSEC_1588_PULSE_OUT2 out J2 AB1 B6 TSEC_1588_ALARM_OUT1 out J2 AB1 B7 TSEC_1588_ALARM_OUT2 out J...

Page 41: ...B28 LBC_WE1_N out P40x0 local bus LWE1_N J2 AB1 B29 N C J2 AB1 B30 N C J2 AB1 B31 GND J2 AB1 B32 LBC_LGPL5 in J2 AB1 B33 CPU_IIC1_CLK bidir J2 AB1 B34 CPU_IIC1_DAT bidir J2 AB1 B35 N C J2 AB1 B36 N C...

Page 42: ...ERDES_RX5_N in J2 AB1 B54 CPU_SDHC_CMD bidir J2 AB1 B55 SERDES_RX4_P in J2 AB1 B56 SERDES_RX4_N in J2 AB1 B57 CPU_SDHC_WP in J2 AB1 B58 SERDES_RX3_P in J2 AB1 B59 SERDES_RX3_N in J2 AB1 B60 GND J2 AB2...

Page 43: ...B2 A80 GND J2 AB2 A81 N C J2 AB2 A82 N C J2 AB2 A83 CPU_IIC2_CLK bidir J2 AB2 A84 CPU_IIC2_DAT bidir J2 AB2 A85 CPU_SDHC_DAT3 bidir J2 AB2 A86 N C J2 AB2 A87 N C J2 AB2 A88 CLK_125M_100M_COME_ SDREF1_...

Page 44: ...2 J2 AB2 A104 V12 J2 AB2 A105 V12 J2 AB2 A106 V12 J2 AB2 A107 V12 J2 AB2 A108 V12 J2 AB2 A109 V12 J2 AB2 A110 GND J2 AB2 B61 SERDES_RX2_P in J2 AB2 B62 SERDES_RX2_N in J2 AB2 B63 CPU_SDHC_CD bi J2 AB2...

Page 45: ...6 N C J2 AB2 B77 N C J2 AB2 B78 N C J2 AB2 B79 N C J2 AB2 B80 GND J2 AB2 B81 N C J2 AB2 B82 N C J2 AB2 B83 N C J2 AB2 B84 V5SB J2 AB2 B85 V5SB J2 AB2 B86 V5SB J2 AB2 B87 V5SB J2 AB2 B88 CPU_SPI_CS1_N...

Page 46: ...B103 V12 J2 AB2 B104 V12 J2 AB2 B104 V12 J2 AB2 B106 V12 J2 AB2 B107 V12 J2 AB2 B108 V12 J2 AB2 B109 V12 J2 AB2 B110 GND J3 CD1 A1 GND J3 CD1 A2 LAN2_ACTIVITY_N in J3 CD1 A3 LAN2_MDI_N 3 bidir J3 CD1...

Page 47: ...in J3 CD1 A20 SERDES_RX6_N in J3 CD1 A21 GND J3 CD1 A22 SERDES_RX7_P in J3 CD1 A23 SERDES_RX7_N in J3 CD1 A24 N C J3 CD1 A25 LBC_LAD 10 bidir J3 CD1 A26 LBC_LAD 11 bidir J3 CD1 A27 LBC_LAD 12 bidir J3...

Page 48: ...J3 CD1 A44 N C J3 CD1 A45 N C J3 CD1 A46 CPU_UART4_SOUT out J3 CD1 A47 CPU_UART4_SIN in J3 CD1 A48 N C J3 CD1 A49 N C J3 CD1 A50 EMI1_MDC_COME out J3 CD1 A51 GND J3 CD1 A52 SERDES_RX16_P in J3 CD1 A53...

Page 49: ...N C J3 CD1 B13 N C J3 CD1 B14 N C J3 CD1 B15 CPU_IRQ_OUT out J3 CD1 B16 CPU_IRQ0 in J3 CD1 B17 LBC_CLK0 out J3 CD1 B18 LBC_CLK1 out J3 CD1 B19 SERDES_TX6_P out J3 CD1 B20 SERDES_TX6_N out J3 CD1 B21 G...

Page 50: ...25 bidir J3 CD1 B37 LBC_LA 24 bidir J3 CD1 B38 LBC_LA 23 bidir J3 CD1 B39 LBC_LA 22 bidir J3 CD1 B40 LBC_LA 21 bidir J3 CD1 B41 GND J3 CD1 B42 LBC_LA 20 bidir J3 CD1 B43 LBC_LA 19 bidir J3 CD1 B44 LBC...

Page 51: ...CD2 A62 SERDES_RX19_N in J3 CD2 A63 CPU_EMI2_MDIO bidir J3 CD2 A64 GND J3 CD2 A65 SERDES_RX20_P in J3 CD2 A66 SERDES_RX20_N in J3 CD2 A67 LBC_CS5_N out J3 CD2 A68 SERDES_RX21_P in J3 CD2 A69 SERDES_R...

Page 52: ...88 CPU_GPI0 in J3 CD2 A89 CPU_GPI1 in J3 CD2 A90 GND J3 CD2 A91 IOEXT_GPI5 in J3 CD2 A92 CPU_GPI3 in J3 CD2 A93 GND J3 CD2 A94 CPU_GPI4 in J3 CD2 A95 IOEXT_GPI6 in J3 CD2 A96 GND J3 CD2 A97 IOEXT_GPI7...

Page 53: ...C out J3 CD2 B64 LP_TMP_DET_BAT out J3 CD2 B65 SERDES_TX20_P out J3 CD2 B66 SERDES_TX20_N out J3 CD2 B67 GND J3 CD2 B68 SERDES_TX21_P out J3 CD2 B69 SERDES_TX21_N out J3 CD2 B70 GND J3 CD2 B71 SERDES_...

Page 54: ...ND J3 CD2 B88 CPU_GPO0 out J3 CD2 B89 CPU_GPO1 out J3 CD2 B90 GND J3 CD2 B91 IOEXT_GPO5 out J3 CD2 B92 CPU_GPO3 out J3 CD2 B93 GND J3 CD2 B94 CPU_GPO4 out J3 CD2 B95 IOEXT_GPO6 out J3 CD2 B96 GND J3 C...

Page 55: ...tion and Use 6806800R95B 55 J3 CD2 B104 V12 J3 CD2 B105 V12 J3 CD2 B106 V12 J3 CD2 B107 V12 J3 CD2 B108 V12 J3 CD2 B109 V12 J3 CD2 B110 GND Table 3 4 COMX AB CD Connectors continued Connector refdes C...

Page 56: ...Controls LEDs and Connectors COMX P40x0 ENP2 Installation and Use 6806800R95B 56...

Page 57: ...to support the QorIQ P4040 P4080 integrated processor at 1 2GHz core frequency Currently productized variants support up to 4GB of DDR3 soldered down The QorIQ P4080 integrated communication processor...

Page 58: ...Functional Description COMX P40x0 ENP2 Installation and Use 6806800R95B 58 4 2 Block Diagram Figure 4 1 COMX P40x0 ENP2 Block Diagram...

Page 59: ...r Supervisor and Hypervisor instruction level privileges APU classic double precision floating point unit 128 Kbyte private L2 cache running at the same frequency of CPU 2 Mbyte of shared L3 CoreNet p...

Page 60: ...ernate Linux filesystem The local bus is also extended to the COM Express connectors There are six chip select signals supported CS0 CS1 and CS3 6 CS0 is reserved for the boot device and defaults to t...

Page 61: ...device tree blob RAMDISK image and FMAN ucode image The detailed map is described in the following table Table 4 1 NOR FLASH Map Block Blocks Start End Size Description 0 1 0000 0000 0001 FFFF 128 KB...

Page 62: ...COM Express connector as SERDES 16 19 Bank 3 also routes 4 lanes to the COM Express connector but is unused for this module Bank 1 provides 2 additional SERDES lanes on board for CPU debugging through...

Page 63: ...1 Reserved2 0x0F 100MHz3 125MHz3 6 PCIe1 x4 2 5Gbps SGMII FM2 x4 1 25Gbps XAUI FM2 3 125Gbps 1 Reserved2 0x0F 100MHz3 125MHz3 7 SRIO2 x4 3 125Gbps SRIO1 x4 3 125Gbps PCIe3 x4 2 5Gbps 1 SGMII FM1 x4 1...

Page 64: ...Functional Description COMX P40x0 ENP2 Installation and Use 6806800R95B 64 The following figure illustrates the distribution of SERDES lanes on the module Figure 4 3 Distribution of SERDES Lanes...

Page 65: ...re A thermal diode is integrated in the P40x0 which connects to a thermal sensor ADT7411 The CPU can get the junction temperature via I2C When the junction temperature reaches105o C the ADT7411 drives...

Page 66: ...1200 MT s Each channel consists of 64 bit data and 8 bit ECC The module supports either 1GB or 2GB of on board memory per channel for a total of 2GB or 4GB Each memory bank consists of 9 memory chips...

Page 67: ...0 512MB PCIE3 MEM 7 E000 0000 F E000 0000 1000 0000 256MB LBC NOR FLASH 8 F000 0000 F F000 0000 0040 0000 4MB DCSR 9 F400 0000 F F400 0000 0020 0000 2MB BMAN MEM 10 F420 0000 F F420 0000 0020 0000 2MB...

Page 68: ...E connectors CPU_GPIO7 GPO4 of COME connectors CPU_GPIO19 Clock generators enable control CPU_GPIO20 Carried board reset output CPU_GPIO23 Clock generator of bank 1 frequency selection CPU_GPIO24 Cloc...

Page 69: ...nd 24 are multiplexed with other functional blocks The pins should be configured as follows GPIO19 RCW DMA1 1b GPIO20 RCW DMA2 10b GPIO23 24 RCW IRQ 1b After reset the direction for all GPIOs are set...

Page 70: ...odefinewhetheranSDcardorMicroSDcardispopulated on the carrier board 4 11 SPI Interface The COMX P40x0 ENP2 provides a SPI bus from the P40x0 CPU with 3 chip select signals All SPI bus signals are rout...

Page 71: ...it Ethernet option should set RCW EC1 to 00 to select RGMII operation 4 12 1 MDIO There are two groups of MDIO buses in the P40x0 CPU The first group called EMI1 complies with IEEE 802 3 Clause 22 and...

Page 72: ...led EMI2 which complies with IEEE 802 3ae Clause 45 and is used for management of SERDES connections configured for 10GE XAUI EMI2 has two pins EMI2_MDC and EMI2_MDIO External PHY access is performed...

Page 73: ...15 Real Time Clock The RTC is implemented by an ST Micro M41T62LC6F device It is accessed over I2C bus 2 of the P40x0 CPU at address 0xD0 The RTC provides a 32 KHz clock output to the CPU for timekee...

Page 74: ...on the same CPU pins An active low overcurrent signal USB_OC_4_5_N is provided from the COM Express connector to indicate a power fault on the fifth USB port It is routed as an interrupt to the CPU 4...

Page 75: ...istribution of I2C buses Table 4 8 I2C Interface Address Bus Component Function 0xDC I2C1 9FG104DGILFT Clock Generator 0xD0 I2C1 M41T65Q6F Watchdog 0x30 I2C1 PCA9557PW T IO Expander 0xAC I2C1 MCP98243...

Page 76: ...located on I2C1 one is for ID EEPROM U30 AT24C02C storing board serial number MAC address and so on and the other is for Processor EEPROM U2001 AT24C512C storingprocessorIDandsoon TheI2Caddressesofthe...

Page 77: ...ed via strap pins or SMBus control By default strap pins are used The input clock for the first clock generator is 25MHz and three differential output pairs are provided First pair are connected to Se...

Page 78: ...Functional Description COMX P40x0 ENP2 Installation and Use 6806800R95B 78...

Page 79: ...figuration is selected For proper settings refer SERDES Block on page 62 Figure 5 1 Clock Distribution Table 5 1 Configuration of the frequency of SERDES reference clock by carrier SERDES bank 1 refer...

Page 80: ...S reference clock by GPIO SERDES bank 1 reference clock SERDES bank 2 reference clock CPU_GPIO23 0 100MHz CPU_GPIO24 0 100MHz CPU_GPIO23 1 125MHz CPU_GPIO24 1 125MHz Default 100MHz Default 125MHz Tabl...

Page 81: ...verview This subsection describes the power supply system for the module 12V Power is supplied to module from ATX type using Artesyn carrier power supply through COM Express connectors and on board re...

Page 82: ...the COMX P40x0 ENP2 differs between secure boot mode and non secure boot mode For secure boot mode POVDD should be set to 1 5V DC and is powered at least 100 system clock cycles after the rising edge...

Page 83: ...o the network The IP address should 192 168 0 100 The TFTP root is tftpboot You need to create a sub directory named comx_p4080 in this root Three copies of the BSP package comx_p4080 COMX_P4080_V100R...

Page 84: ...ed U Boot will not define the environment variable vn If vv includes spaces it should be enclosed within single quote marks For example setenv manufacturer Emerson Network Power saveenv Saves all the...

Page 85: ...der iso mnt 4 Create a opt freescale directory and update access privileges using the following command sudo mkdir p unixopt sdk1 0 sudo chmod a rwx unixopt sdk1 0 5 Change directory to mount using th...

Page 86: ...d P4080 which contains SCP P4080 2G ENP2 source code Table 7 2 BSP Source Code Package Layout File Directory Name Description build sh Top script for building all of BSP images for BSP release It call...

Page 87: ...PATH build_p4080ds_release sysroots i686 linux usr bin 7 6 2 Network Variables This table lists example network u boot environment variables to establish a network connection By default the factory se...

Page 88: ...uImage setenv norfsfile comx_p4080 COMX_P4080_V100R00 rootfs_ext2 img setenv fdtfile comx_p4080 COMX_P4080_V100R00 comx dtb setenv ubootfile comx_p4080 COMX_P4080_V100R00 u boot bin setenv nandfsfile...

Page 89: ...is 1000000 fdtaddr Default is C0000 ramdiskaddr Default is 2000000 Device Variables setenv ethact FM1 DTSEC1 setenv netdev eth0 setenv uart 0 setenv consoledev ttyS0 setenv baudrate 115200 setenv usb...

Page 90: ...ate hwbootargs Default is riohdid 0 xauiphy 1 generated by U Boot based on hwcon fig othbootargs Default is ramdisk_size 00700000 cache sram size 0x10000 Bootup Variables ramboot Default is setenv boo...

Page 91: ...k hostname netdev off mmcfatboot default is setenv bootargs root dev mmcbdev rw rootdelay 30 console consoledev baudrate hwbootargs othbootargs mmcinfo fatload mmc 0 1 loadaddr boot bootfile fatload m...

Page 92: ...es 3 4 MiB Load Address 00000000 Entry Point 00000000 Verifying Checksum OK In the kernel boot up message Linux version 2 6 34 6 ec7536 cncdebaobs04 emrsn org gcc version 4 3 2 Sourcery G Lite 4 3 74...

Page 93: ...X P4080hastheFreescaleQorIQCommunicationsProcessor TheCPUinformationcanbe viewed in the terminal Figure 7 1 below shows console output containing an example of the CPU information CPU0 is the active C...

Page 94: ...ss 36 bit Phyiscal Base Address Size Description 1 0000 0000 0 0000 0000 8000 0000 2 GB DDR3 Memory 2 8000 0000 C 0000 0000 2000 0000 512 MB PCIE1 MEM 3 A000 0000 C 2000 0000 2000 0000 512 MB PCIE2 ME...

Page 95: ...t Both areas are used to store critical data by U Boot 12 F801 0000 F F801 0000 0001 0000 64 KB PCIE2 IO 13 F802 0000 F F802 0000 0001 0000 64 KB PCIE3 IO 14 FFA0 0000 F FFA0 0000 0010 0000 1 MB NAND...

Page 96: ...R Chip Select Interleaving Mode CS0 CS1 Table 7 4 GPIO States GPIO Input Output Reset State Description GPIO00 I I GPI0 of COM E connectors GPIO01 I I GPI1 of COM E connectors GPIO02 I I GPI3 of COM E...

Page 97: ...ransmitters UART in the COMX P40x0 each with Tx and Rx signals routed to the COM E connectors Table 7 5 GPIO Command Usage Command Description gpio dump Dumps the direction od and level information fo...

Page 98: ...B and has 1024 uniform blocks of 128 K or 64 K words each The 36 bit physical address of NOR Flash is 0xFE8000000 0xFEFFFFFFF Boot up message in U Boot is FLASH 128 MiB NOR Flash supports the followin...

Page 99: ...B of data with 4 KB spare making a total of 8192 blocks NAND Flash supports the following commands protect on all Protects all flash banks protect off start end Makes flash from address start to addre...

Page 100: ...s NAND by erasing bad blocks Considered unsafe nand markbad off Marks bad block or blocks at offset Considered unsafe nand biterr off Makes a bit error at offset Considered unsafe Table 7 7 NAND Flash...

Page 101: ...r of network ports MAC addresses errata level manufacturing date and other information Boot up message in the U Boot will be EEPROM NXID v0 U Boot provides several mac utilities to display and program...

Page 102: ...cessor family module family and configuration among others Boot up message in U Boot will appear as EEPROM COMX The U Boot provides brd utilities to display and program the data in BOARD EEPROM mac er...

Page 103: ...e 7 15 3 Real Time Clock RTC and Watchdog Timer WDT COMX P40x0 uses RTC and Watchdog features on M41ST85W The I2C RTC WDT M41ST85W U12 is adopted on the COMX P40x0 and located on I2C 1 Boot up message...

Page 104: ...2 01 Wednesday Time 17 59 00 U Boot provides wdt commands to operate on the WDT features The following are usage examples of wdt for the COMX P40x0 wdt status WDT disabled wdt enable 5 WDT enabled wit...

Page 105: ...romtheP40x0CPUwith3chip selectsignals AllSPI bus signals are routed to COM Express connectors For more information on the distribution of the SPI bus see SPI Interface on page 70 U Boot provides sf ut...

Page 106: ...Express connector The hub is hardware strapped to indicate all ports removable Two active low overcurrent signals are received from the COM Express connector to the USB hub to indicate power faults U...

Page 107: ...ectors Utility Function usb reset Resets or rescans USB controller usb stop f Stops USB f force stop usb tree Shows USB device tree usb info dev Shows available USB devices usb storage Shows details o...

Page 108: ...on to activate the SerDes RCW option Power off the board For RCW options 7 or 8 a means to change the SERDES clock settings must be provided by the customer s carrier board Power up the board rcw list...

Page 109: ...lation and Use 6806800R95B 109 Using option 5 from Table Options of the SERDES routed to COM Express Connectors on page 63 as an example the boot up message will appear as below Figure 7 2 Example of...

Page 110: ...twork ports in the frame managers 1 RGMII FM1 XAUI FM2 RCW options 1 4 9 11 12 1 RGMII FM1 4 SGMII FM2 RCW options 5 6 1 RGMII FM1 only SRIO configuration RCW options 7 8 PCIE basednetworkportslikethe...

Page 111: ...ion of SerDes RCW Option Onboard RGMII SGMII Riser XAUI Riser PRO 1000 dual port 1 PRO 1000 dual port 2 1 FM1 DTSEC1 X SLOT J10 FM2 DTGEC1 SLOT J6 e1000 0 e1000 1 SLOT J14 e1000 2 e1000 3 2 FM1 DTSEC1...

Page 112: ...below 8 FM1 DTSEC1 X X SLOT J6 e1000 0 e1000 1 X 9 FM1 DTSEC1 X SLOT J10 FM2 DTGEC1 X X 10 FM1 DTSEC1 SLOT J10 FM2 DTSEC1 FM2 DTSEC2 FM2 DTSEC3 FM2 DTSEC4 X X X 11 FM1 DTSEC1 X SLOT J10 FM2 DTGEC1 SLO...

Page 113: ...l it in SLOT J14 and for Freescale XAUI Riser install it in SLOT J10 The U Boot boot up message will list the valid ports list FM1 DTSEC1 FM2 DTSEC1 FM2 DTSEC2 FM2 TGEC1 e1000 0 e1000 1 The ethX list...

Page 114: ...ou need to create this directory and provide full privileges for all users to access Use the following commands to create directory and provide privileges sudo mkdir p sudo chmod a rwx local local tmp...

Page 115: ...d for code warrior to burn image to NOR Flash rootfs_ext2 img RAMDISK image rootfs_nfs tar gz NFS rootfs u boot bin U Boot uImage Linux kernel image 7 21 1 Build U Boot The U Boot is based on SDK1 0 w...

Page 116: ...clean cleans the kernel dtb compiles device tree binary Output The build images are uImage and comx dtb in the current working directory 7 21 3 Build ROOTFS The rootfs for SCP P4080 2G ENP2 include R...

Page 117: ...t Steps The following steps must be performed before deployment 1 Connect the board to your network using a network cable to the RGMII Ethernet port 2 Setup a TFTP server in this network Assuming that...

Page 118: ...ipaddr 192 168 0 99 setenv netmask 255 255 255 0 setenv gatewayip 192 168 0 1 setenv serverip 192 168 0 100 setenv ethact FM1 DTSEC1 12 Setup the U Boot environment variables for upgrade files Example...

Page 119: ...dt run upduboot 2 Erase previous U Boot environment settings using the run eraenv command 3 Reset the board using the reset command The board will boot up with new BSP 7 23 Boot COMX P40x0 provides th...

Page 120: ...following are examples of critical environment variables 7 23 2 NORboot COMX P40x0 has a U Boot variable called norboot setenv bootargs root dev ram rw console consoledev baudrate hwbootargs othbootar...

Page 121: ...om NOR flash into RAM and then boot JFFS2 will then mount on the file system on NAND flash as rootfs The following are the critical environment variables for nandboot Below are examples of critical en...

Page 122: ...ill then mount on the remote server as rootfs The following are the critical environment variables for nfsboot Below are examples of critical environment variables 7 23 5 USBFATboot and USBEXT2boot CO...

Page 123: ...tion will be mounted on the USB stick as rootfs The usbext2boot will load Linux kernel and DTB from the EXT2 partition 2nd partition on USB stick into RAM and then boot Mounting it on the same partiti...

Page 124: ...to RAM and then boot EXT2 partition 2nd partition will mount on this card as rootfs mmcext2boot will load Linux kernel and DTB from the EXT2 partition 2nd partition on MMC SDHC card into RAM and then...

Page 125: ...Artesyn sales office For released products you can also visit our Web site for the latest copies of our product documentation 1 Go to www artesyn com computing 2 Under SUPPORT click TECHNICAL DOCUMENT...

Page 126: ...Related Documentation COMX P40x0 ENP2 Installation and Use 6806800R95B 126...

Page 127: ...ation ask your Artesyn representative The product has been designed to meet the standard industrial safety requirements It must not be used except in its specific area of office telecommunication indu...

Page 128: ...COMX P40x0 ENP2 Installation and Use 6806800R95B Safety Notes 128...

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Page 130: ...syn and the Artesyn Embedded Technologies logo are trademarks and service marks of Artesyn Embedded Technologies Inc All other product or service names are the property of their respective owners 2014...

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