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Maps and Registers

146

ATCA-7540 Installation and Use (6806871A01A

)

5.1.12.11 DIMM ADR Status Register

BIOS can read the status of PCH_ADR_IRQ_ signal from this register on boot up. This gives BIOS 
the information that the DIMM has data stored from last boot. BIOS must clear this register 
after boot up. Writing “1” to this register bit clears the register bit.       

5.1.13 CPU Control Register

The following table contains the CPU Control Register information. 

Table 5-63.  DIMM ADR Status Register

Address Offset: 0x1A

Bit

Description

Default

Access

0

Indicates if the ADR feature is enabled. (GPIO37 of 
Cavecreek) 
0: ADR disabled (PCH_ADR_IRQ_ is driven high)
1: ADR enabled (PCH_ADR_IRQ_ is driven low)

PWR_GOOD:0

LPC: r/w1c
IPMC: r

7:1

Reserved 0

r

Table 5-64.  CPU Control Register

Address Offset: 0x1E

Bit

Description

Default

Access

0

PCH_PSTATE_ pulse generation. Minimum low pulse 
width is X 

μ

s:

0: No action
1: Generate PSTATE low pulse

-

IPMC:  w

1

PCH_RCIN_ pulse generation. Minimum low pulse 
width is X 

μ

s:

0: No action
1: Generate RCIN low pulse

-

IPMC:  w

7:2

Reserved -

-

Summary of Contents for ATCA-7540

Page 1: ...ATCA 7540 Installation and Use P N 6806871A01A December 2018 ...

Page 2: ...onal use or referenced in another document as a URL to an Artesyn website The text itself may not be published commercially in print or electronic form edited translated or otherwise altered without the permission of Artesyn It is possible that this publication may contain reference to or information about Artesyn products machines and programs programming or services that are not available in you...

Page 3: ... 2 1 Unpacking and Inspecting the Blade 45 2 2 Environmental and Power Requirements 45 2 2 1 Environmental Requirements 46 2 2 2 Power Requirements 49 2 3 Blade Layout 51 2 4 Switch Settings 52 2 5 Installing the Blade Accessories 54 2 5 1 RDIMM Memory Modules 54 2 5 2 M 2 NVMe or SATA Modules 57 2 6 Installing and Removing the Blade 58 2 6 1 Installing the Blade 58 2 6 2 Removing the Blade 61 2 7...

Page 4: ... I O Controller Features 85 4 4 2 Intel i350 Quad GB Ethernet Controller 86 4 4 3 Firmware Flashes 86 4 5 ATCA Fabric Interface Ethernet Controller 86 4 6 Storage Controller 87 4 6 1 ATCA Update Channels 87 4 7 M 2 NVMe SATA Modules 89 4 8 Heat Sink 89 4 9 BIOS 89 4 10 IPMC 89 4 10 1 I C Bus 90 4 10 2 FRU Data Serial IDROM 91 4 10 3 System Event Log EEPROM 91 4 11 Serial Redirection 92 4 12 Serial...

Page 5: ...ster Map 110 5 1 4 1 UART Register Overview 110 5 1 4 2 UART Registers DLAB 0 111 5 1 4 3 Programmable Baud Rate Generator 124 5 1 5 FPGA Register Mapping 125 5 1 5 1 LPC I O Register Map 125 5 1 5 2 IPMC I C Register Map 126 5 1 6 Module Identification Register 129 5 1 7 Version Register 129 5 1 8 Serial Redirection Control Register 129 5 1 9 Serial over LAN Control Register 130 5 1 10 Serial Lin...

Page 6: ...tatus Register 149 5 1 15 3 Telecom Interrupt Control Register 150 5 1 15 4 RTM Interrupt Status Register 150 5 1 15 5 External Interrupt Status Register 150 5 1 15 6 Interrupt Mask and Map Registers 151 5 1 16 PCI Express Hot Plug I C I O Expander Registers 153 5 1 16 1 CPU0 Hot Plug I C I O Expander Registers 153 5 1 16 2 CPU1 Hot Plug I C I O Expander Registers 153 5 1 16 3 Hot Plug Virtual Pin...

Page 7: ...t Type 174 6 4 3 Supported Boot Devices 174 6 4 4 Selecting the Boot Device 174 6 5 iSCSI Boot 177 6 6 IPMI Boot Parameter 181 6 7 BIOS Setup Configuration 183 6 7 1 Main 183 6 7 2 Advanced 184 6 7 2 1 Platform Information 185 6 7 2 2 RTM Configuration 186 6 7 2 3 Peripheral Configuration 188 6 7 2 4 NVM Express Information 190 6 7 2 5 USB Configuration 190 6 7 2 6 Socket Configuration 191 6 7 2 7...

Page 8: ...ool 226 7 4 Establishing an SOL Session 228 8 Supported IPMI Commands 229 8 1 Standard IPMI Commands 229 8 1 1 Global IPMI Commands 229 8 1 2 System Interface Commands 229 8 1 3 Watchdog Commands 230 8 1 4 SEL Device Commands 230 8 1 5 FRU Inventory Commands 231 8 1 6 Sensor Device Commands 231 8 1 7 Chassis Device Commands 232 8 1 7 1 System Boot Options Commands 233 8 1 8 LAN Device Commands 249...

Page 9: ...load Communication Time Out Command 268 8 4 12 Enable Payload Control Command 269 8 4 13 Disable Payload Control Command 269 8 4 14 Reset IPMC Command 270 8 4 15 Hang IPMC Command 270 8 4 16 Graceful Reset Command 271 8 4 17 Get Payload Shutdown Time Out Command 271 8 4 18 Set Payload Shutdown Time Out Command 272 8 4 19 Get Module State Command 273 8 4 20 Enable Module Site Command 274 8 4 21 Dis...

Page 10: ...ailure Sensor 306 9 4 9 Payload Power Failure State Sensor 306 9 4 10 Payload Power Failure Cause Sensor 306 9 5 Power On Self Test POST 307 9 6 Ejector Handle De Bounce 307 9 7 FRU Inventory 308 9 7 1 MAC Address FRU OEM Records 308 9 8 Reset and Power Domain 310 9 9 Power Configuration 311 9 10 BIOS Boot Configuration Parameters 311 9 11 Asynchronous Event Notification 313 9 12 Serial Line Selec...

Page 11: ...Contents ATCA 7540 Installation and Use 6806871A01A 11 A Related Documentation 321 A 1 Artesyn Embedded Technologies Documentation 321 A 2 Related Specifications 321 ...

Page 12: ...12 ATCA 7540 Installation and Use 6806871A01A Contents ...

Page 13: ...10 P23 Backplane Connector Pinout Rows E to H 78 Figure 3 11 P30 Backplane Connector Pinout Rows A to D 79 Figure 3 12 P30 Backplane Connector Pinout Rows E to H 79 Figure 3 13 P31 Backplane Connector Pinout Rows A to D 80 Figure 3 14 P31 Backplane Connector Pinout Rows E to H 80 Figure 3 15 P32 Backplane Connector Pinout Rows A to D 81 Figure 3 16 P32 Backplane Connector Pinout Rows E to H 81 Fig...

Page 14: ...e 6 21 CPU P State Control 198 Figure 6 22 CPU C State Control 199 Figure 6 23 Package C State Control 200 Figure 6 24 Console Redirection 201 Figure 6 25 APEI Configuration 202 Figure 6 26 IPMI OEM Configuration 203 Figure 6 27 Security Configuration 205 Figure 6 28 Boot Configuration 206 Figure 6 29 EFI Boot Order 208 Figure 6 30 Legacy Boot Order 209 Figure 6 31 Exit Menu 210 Figure 7 1 SOL Ove...

Page 15: ...e 4 5 SMBus Address Map 98 Table 5 1 Register Default 101 Table 5 2 Register Access Type 101 Table 5 3 LPC I O Register Map Overview 102 Table 5 4 IPMC SPI Register 103 Table 5 5 POST Code Register 103 Table 5 6 Super IO Configuration Index Register 104 Table 5 7 Super IO Configuration Data Register 104 Table 5 8 Global Configuration Register Summary 105 Table 5 9 Super IO Logical Device Number Re...

Page 16: ...B Register DLL if DLAB 1 125 Table 5 37 Divisor Latch MSB Register DLM if DLAB 1 125 Table 5 38 FPGA Register Map Overview 126 Table 5 39 Module Identification Register 129 Table 5 40 FPGA Version Register 129 Table 5 41 Serial Redirection Control Register 129 Table 5 42 Serial over LAN Control Register 130 Table 5 43 Serial Line Routing Register 131 Table 5 44 ME Power Failure State Register 132 ...

Page 17: ...for PCA9555 Internal Register 155 Table 5 76 Content of PCA9555 Internal Register 155 Table 5 77 Flash Status Register 156 Table 5 78 PCH Output Enable Register 157 Table 5 79 RTM SPI Address Command Register 158 Table 5 80 RTM SPI Write Register 158 Table 5 81 RTM SPI Read Register 158 Table 5 82 Update Channel Equalization Control Register 159 Table 5 83 RTM USB Control Register 160 Table 5 84 R...

Page 18: ...6 Advanced Peripheral Configuration Intel VT for Directed I O VT d 189 Table 6 7 Advanced USB Configuration 191 Table 6 8 Processor Configurations 192 Table 6 9 Per Socket Configuration 194 Table 6 10 Common RefCode Configuration 195 Table 6 11 Memory Configuration 196 Table 6 12 Memory RAS Configuration 197 Table 6 13 CPU P State Control 198 Table 6 14 CPU C State Control 199 Table 6 15 Package C...

Page 19: ... 8 19 Request Data of Set Serial Output Command 252 Table 8 20 Response Data of Set Serial Output Command 252 Table 8 21 Request Data of Get Serial Output Command 253 Table 8 22 Response Data of Get Serial Output Command 254 Table 8 23 Feature Configuration Command 254 Table 8 24 Set Feature Configuration Command 255 Table 8 25 Feature Selector Assignments 256 Table 8 26 Get Feature Configuration ...

Page 20: ...Module Site Command Description 274 Table 8 49 Disable Module Site Command Description 274 Table 8 50 Reset Carrier SDR Repository Command Description 275 Table 9 1 HPM 1 Components 282 Table 9 3 Event Data of Boot Bank Sensor 302 Table 9 4 Status Sensor s Sensor Reading 303 Table 9 5 Voltage and Temperature Sensor Devices 304 Table 9 6 FRU Information and SEL at EEPROM Storage 308 Table 9 7 Artes...

Page 21: ...stallation on page 45 outlines the installation requirements hardware accessories switch settings installation and removal procedures Controls Indicators and Connectors on page 67 describes external interfaces of the blade This includes connectors and LEDs Functional Description on page 83describes the functional blocks of the blade in detail This includes a block diagram description of the main c...

Page 22: ...asic Blade Services BIOS Basic Input Output System CPU Central Processing Unit DDR Double Data Rate DIMM Dual Inline Memory Module DLAB Divisor Latch Access Bit DMI Direct Media Interface eNVM Embedded Non Volatile Memory ECC Error Correction Code EEPROM Electrically Erasable Programmable Read only Memory EMC Electromagnetic Compatibility EMV Elektromagnetische Vertraeglichkeit ESD Electrostatic D...

Page 23: ...MB Intelligent Platform Management Bus IPMC Intelligent Platform Management Controller IPMI Intelligent Platform Management Interface IS In Service KCS Keyboard Controller Style LAN Local Area Network LED Light emitting Diode LGA Land Grid Array LPC Low Pin Count MAC Media Access Control ME Management Engine MMC Module Management Controller NCSI Network Controller Sideband Interface NEBS Network E...

Page 24: ...t Control Interface PEM Power Entry Module PICMG PCI Industrial Computer Manufacturers Group PIM Power Input Module POST Power On Self Test PROM Programmable Read only Memory PXE Preboot eXecution Environment QSFP Quad Small Form factor Pluggable RAS Reliability Availability and Serviceability RMCP Remote Management Control Protocol RDIMM Registered Dual Inline Memory Module RTC Real Time Clock RT...

Page 25: ...agement Bus SMI Serial Management Interface SOL Serial over LAN SPD Serial Presence Detect SPI Serial Peripheral Interface SSC Spread Spectrum Clocking SSD Solid State Device TPM Trusted Platform Module UART Universal Asynchronous Receiver Transmitter UEFI Unified Extensible Firmware Interface UPI Ultra Path Interconnect USB Universal Serial Bus VLP Very Low Profile VGA Video Graphics Adapter Abbr...

Page 26: ... body text Courier Bold Used to characterize user input and to separate it from system output Reference Used for references and for table and figure descriptions File Exit Notation for selecting a submenu text Notation for variables and keys text Notation for software buttons to click on the screen and parameter description Repeated item for example node 1 node 2 node 12 Omission of information fr...

Page 27: ...editions Indicates a hazardous situation which if not avoided may result in minor or moderate injury Indicates a property damage message NOTICE No danger encountered Pay attention to important information Helpful information and tips Notation Description Part Number Publication Date Description 6806871A01A December 2018 Initial Version ...

Page 28: ...About this Manual 28 ATCA 7540 Installation and Use 6806871A01A ...

Page 29: ...l engineering are authorized toinstall remove ormaintain the product The information given in thismanual is meant to complete the knowledge of a specialist and must not be used as replacement for qualified personnel Keep away from live circuits inside the equipment Operating personnel must not remove equipment covers Only factory authorized service personnel or other qualified service personnel ma...

Page 30: ...o cables should be connected to these ports Cables attached to these ports during maintenance must not exceed a length of 10 feet 3 meters This is a Class A product based on the standard of the Voluntary Control Council for Interference VCCI by Information Technology Interference If this equipment is used in a domestic environment radio disturbance may arise When such trouble occurs the user may b...

Page 31: ...faces are designed for use as intra building interfaces only Type 2 or Type 4 ports as described in GR 1089 and require isolation from the exposed OSP cabling The addition of primary protectors is not sufficient protection in order to connect these interfaces metallically to OSP wiring The intra building port s of the equipment or subassembly must use shielded intra building cabling wiring that is...

Page 32: ...emains powered even if it is disconnected from the power supply circuit and vice versa To avoid damage or injuries always check that there is no voltage on the line that has been disconnected before continuing your work The EMI radiation compliancy of the product has been qualified in a reference system with the Spread Spectrum feature disabled Please note that the integrator needs to verify the E...

Page 33: ...er wavelength visibility pulse duration applicable standards prior to servicing equipment Do not look at laser device with an optical instrument at any time Battery Blade Damage Incorrect battery installation may result in a hazardous explosion and blade damage Alwaysusethesametypeoflithiumbattery asisinstalled andmake sure the batteryisinstalled as described in the manual Environment Improper dis...

Page 34: ...Safety Notes 34 ATCA 7540 Installation and Use 6806871A01A ...

Page 35: ...ss es die Anforderungen für die von der Industrie geforderten Sicherheitsvorschriften erfüllt Es darf nicht in sicherheitskritischen Komponenten lebenserhaltenden Geräten oder in Flugzeugen verwendet werden Einbau Wartung und Betrieb dürfen nur von durch Artesyn ausgebildetem oder im Bereich Elektronik oder Elektrotechnik qualifiziertem Personal durchgeführt werden Die in diesem Handbuch enthalten...

Page 36: ...einem konformen System erforderlich Um sicherzustellen dass die Einhaltung der entsprechenden Vorschriften für die Funkfrequenzen einghalten werden verwenden Sie beim Anschlieeßen von Peripheriegerätennurabgeschirmte Kabel Zurordnungsgemäßen EMV Abschirmung istdas System nur mit installierten Frontblenden zu betreiben und alle freien Steckplätze sind abzudecken oder mit Steckkarten zu fuellen Die ...

Page 37: ...nd von Zusatzmodulen Lesen Sie daher vor der Installation von Zusatzmodulen die zugehörige Dokumentation Fehlerhafte Installation von Zusatzmodulen kann zur Beschädigung des Blades und der Zusatzmodule führen Beschädigung des Systems Warnung Die Gebäude internen Schnittstellen intra building ports per GR 1089 CORE der Geräte oder Baugruppen sind nur für gebäudeinterne Verkabelung vorgesehen Die Sc...

Page 38: ...ie das Produkt mit den Schrauben an der Frontplatte im System Stellen Sie sicher dass das Produkt vollständig vom Gehäuse abgeschirmt ist Datenschaden Wenn die Stromversorgung des Geräts während eines Firmware Updates des Flash Memory des Geräts unterbrochen wird werden die Änderungen nicht gespeichert oder der Flash Memory kann beschädigt werden In diesem Fall bleibt das Produkt wahrscheinlich in...

Page 39: ...rden Überprüfen und ändern Sie die Schaltereinstellung die nicht mit Reserved gekennzeichnet sind bevor Sie das Blade installieren Beschädigung des Blades Überprüfen und ändern Sie die Schaltereinstellung bevor Sie das Blade installieren Das Verstellen von Schaltern während des laufenden Betriebes kann zur Beschädigung des Blades führenn Laser Verletzungsgefahr Wenn ein Etikett mit der Aufschrift ...

Page 40: ...chädigungen des Blades zur Folge haben Verwenden Sie deshalb nur den Batterietyp der auch bereits eingesetzt wurde und befolgen Sie die Installationsanleitung Umweltschutz Unsachgemäße Entsorgung von gebrauchten Produkten kann die Umwelt schädigen Entsorgen Sie gebrauchte Produkte stets gemäß der in Ihrem Land gültigen Gesetzgebung und den Empfehlungen des Herstellers ...

Page 41: ...f memory 8 GB 16 GB and 32 GB DDR4 modules in Very Low Profile VLP available Single slot ATCA form factor Direct CPU to PCI Express PCIe interface providing 48 PCIe Gen3 lanes 8 Gbps Next Generation Communications Platform from Intel with on board Intel Lewisburg Platform Controller Hub PCH 10 GbE controller PCH SKU with QuickAssist Accelerators Optional Dual Gigabit Ethernet AdvancedTCA Base Inte...

Page 42: ...gn 40 C ambient environment the ATCA 7540 MTBF is 362 000 hours at 60 confidence level This does not include the RDIMM or M 2 modules The MTBF for twelve 16 GB RDIMM modules is 197 000 hours The MTBF for a single M 2 SSD module is 1 483 000 hours Contact Artesyn for alternate environments or temperatures Table 1 1 Mechanical Data Feature Value Dimensions width x height x depth 30 mm x 351 mm x 312...

Page 43: ...Introduction ATCA 7540 Installation and Use 6806871A01A 43 1 4 Product Identification The following figure shows the location of the serial number label Figure 1 1 Serial Number Location Serial Number ...

Page 44: ... 40G B 4 FASTENER BOM controlled ATCA 7540 64GB L ATCA PACKETPROCESSING BLADE DUAL INTEL XEON SERVER 4114T SILVER 10 CORE 85 W 2 2 GHZ 8 x 8 GB DIMMS 40G B4 ATCA 7540 C06 ATCA PACKET PROCESSING BLADE DUAL INTEL XEON SERVER 5119T GOLD 14 CORE 85 W 1 9 GHZ 12X DIMM SOCKETS 192 GB 1 TB M 2 40G B 4 FASTENER BOM controlled ATCA 7540 D ATCA PACKET PROCESSING BLADE DUAL INTEL XEON SERVER 5119T GOLD 14 CO...

Page 45: ...com 3 Removethedesiccantbagshippedtogetherwiththebladeanddisposeofitaccording to your country s legislation 2 2 Environmental and Power Requirements In order to meet the environmental requirements the blade has to be tested in the system in which it is to be installed NOTICE Damage of Circuits Electrostaticdischargeandincorrectbladeinstallationandremovalcandamagecircuits or shorten their life Befo...

Page 46: ...mental requirements of the blade may be further limited due to installed accessories such as hard disks or mezzanine modules with more restrictive environmental requirements Operating temperatures refer to the temperature of the air circulating around the blade and not to the actual component temperature Blade Damage Blade Surface High humidity and condensation on the blade surface causes short ci...

Page 47: ...lled accessories Forced Air Flow Air Volume Pressure Loss Reference to see level 40 CFM NA Temperature Change 0 5 C min according to Telcordia GR 63 CORE 1 C min Relative Humidity Normal Operation 5 RH to 85 RH non condensing ExceptionalOperation 5 RHto95 RH non condensing According to Telcordia GR 63 CORE NEBS and EN 300 019 1 3 Classes 3 1 and 3 1E 5 to 95 non condensing according to Telcordia G...

Page 48: ... exactly at the given locations Exact locations of critical temperature spots Temperature Spot 1 On the PIM U45 located on top of the transformer Maximum up to 194 o F 90 o C Temperature Spot 2 On the 48 V 12 V DC DC U193 located on the PCB next to the transformer Maximum up to 257 oF 125 oC Shock Half sine 11 ms 98 feet s2 30 m s2 Blade level packaging Half sine 6 ms at 590 feet s2 180 m s2 Free ...

Page 49: ...rther details The blade must be connected to a TNV 2 or a safety extra low voltage SELV circuit A TNV 2 circuit is a circuit whose normal operating voltages exceed the limits for a SELV circuit under normal operating conditions and which is not subject to over voltages from telecommunication networks Table 2 2 Critical Temperature Limits Component CPU Thermal Design Power Max Case or Junction Temp...

Page 50: ...M ATCA 7360 L or RTM ATCA 736x DD 284 W 242 W Without any RTM 272 W 234 W The power consumption has been measured using specific boards in a configuration consideredtorepresenttheworst case maximummemorypopulation 2xM 2NVMeor SATA modules with RTM ATCA 7360 L or RTM ATCA 736x DD and with software simultaneously exercising as many functions and interfaces as possible This includes a particular load...

Page 51: ...the ATCA 7540 Figure 2 2 ATCA 7540 Blade Layout Serial Number P31 P30 P23 P20 P32 Battery J9J3 DIMM G J8J2 DIMM J J9J1 DIMM H 48V to 12V DCDC ATCA PIM RTM 12V Power J5J3 DIMM C J4J2 DIMM A J5J1 DIMM B J1 DIMM F J2J1 DIMM D J1J3 DIMM E J6J4 DIMM K J5J5 DIMM M J6J2 DIMM L M 2 Riser Card CPU0 CPU1 FORTVILLE Intel i350 POWERVILLE PCH ZONE 1 ZONE 2 ZONE 3 ZONE 2 ...

Page 52: ...gure 2 3 Switch Location Top Side of the Blade Table 2 5 Switch SW100 Settings Switch Function Default SW100 1 Payload Power Control OFF Payload power is controlled by IPMC ON Payload power is forced on and IPMC is disabled OFF Payload power is controlled by IPMC SW100 2 Reserved Connected to FPGA OFF Reserved SW100 3 Reserved Connected to FPGA OFF Reserved SW100 4 RTM Power Control OFF RTM power ...

Page 53: ...configuration SW2 4 OFF Reset push button enabled ON Reset push button disabled OFF Enable Faceplate reset push button Table 2 7 Switch SW3 Settings Switch Function Default SW3 1 Manual Default SPI Boot Flash Recovery SPI Boot Flash select enable OFF IPMI selects Boot Flash ON SW3 2 selects Boot Flash OFF IPMI selects Boot Flash SW3 2 SW3 2 controls Boot flash select if SW3 1 is ON OFF Boot from D...

Page 54: ...les The blade provides 12 memory slots for main memory RDIMM modules of type DDR4 VLP You may install and or remove RDIMM memory modules in order to match the main memory size to your needs The corresponding installation removal procedures are described in this section For the location of the RDIMM memory modules see Figure 2 2 ATCA 7540 Blade Layout on page 51 Each processor provides six memory c...

Page 55: ...g in an ESD safe environment NOTICE For optimal performance all memory channels A through M should be populated A balanced RDIMM configuration is recommended that is every CPU uses the same type and amount of RDIMMs The BIOS does not support certain RDIMM modules where the SPD data at offset 0x85 is 97 register and data manufacturer Texas Instruments and offset 0x86 revision 0x0b The only known RD...

Page 56: ...the module carefully into socket As soon as the memory module has been fully inserted the locks automatically close 4 If applicable repeat the steps 2 to 3 to install further modules Removal Procedure To remove an RDIMM module proceed as follows 1 Remove the blade from the system as described in Installing and Removing the Blade on page 58 2 Open the locks of socket at both sides The memory module...

Page 57: ...found via the Technical Documentation search page at https www artesyn com computing search documents If you need to replace the SSD module follow the Removal Procedure below before installing the new SSD module Removal Procedure To remove an M 2 NVMe or SATA module refer to the SSD Module and Hardware Kit NVMe M 2 1TB Quick Start Guide P N 6806868A01 and proceed as follows 1 Remove the blade from...

Page 58: ... 1 Visually inspect the blade and backplane connectors for damage or bent pins before attemptingtoinsertablade Ifanyconnectordamage orpindamageisobserved stop inserting the blade and send the damaged item to proper repair channels 2 Prior to installing the blade into the slot slide the top and bottom latches into the handle release position and pull the handles outward to unlatch the handles from ...

Page 59: ... blade in the card guides of the shelf 4 Apply equal and steady pressure to the blade to carefully slide the blade into the shelf until you feel resistance Continue to push the blade gently until the blade connectors engage 5 Fully insert the blade and turn the handle towards the faceplate The latch automatically slides inwards and locks the handle Latch Handle ...

Page 60: ... Torque the faceplate screws to 0 40 N m NOTE When the blue LED is switched OFF and the green LED IS is switched ON this indicates that the payload has been powered up and the blade is active 7 Connect cables to the faceplate if applicable If you feel that you need an abnormal amount of force during blade insertion into the slot extract the blade then carefully inspect the blade and slot for probl...

Page 61: ...d pull out the handle outward Do not rotate the handle fully outward The blue LED starts blinking indicates that the blade power down process is ongoing 2 Wait until the blue LED is illuminated permanently NOTICE Damage of Circuits Electrostatic discharge incorrect blade installation and removal can damage circuits or shorten their life Before touching the blade or electronic components make sure ...

Page 62: ...d until the blade is detached from the backplane connectors 5 Remove the blade from the shelf 2 7 Replacing the Battery Some blade variants containan on board battery Its location is shown in the following figure NOTICE Data Loss Removing the blade with the blue LED still blinking causes data loss Wait until the blue LED is permanently illuminated before removing the blade A batteryless variant ba...

Page 63: ...Hardware Preparation and Installation ATCA 7540 Installation and Use 6806871A01A 63 Figure 2 4 Location of On board Battery Battery ...

Page 64: ... result in a hazardous explosion Replace the battery as described in this chapter Data Loss If the battery does not provide enough power anymore the RTC is initialized and the data in the NVRAM is lost Replace the battery before four years of actual battery use have elapsed Data Loss Replacing the battery always results in data loss of the devices which use the battery as power backup Back up affe...

Page 65: ...d negative signs NOTICE PCB and Battery Holder Damage Removing the battery with a screw driver may damage the PCB or the battery holder To prevent this damage do not use a screw driver to remove the battery from its holder NOTICE Environmental Damage Improper disposal of used products may harm the environment Always dispose of used products according to your country s legislation and manufacturer ...

Page 66: ...Hardware Preparation and Installation 66 ATCA 7540 Installation and Use 6806871A01A ...

Page 67: ... U3 Table 3 1 Faceplate LEDs LED Description OOS Out Of Service Red optional Amber controllable by IPMC This LED is controlled by higher layer software such as middle ware or applications IS In Service Payload Power Status Green The payload power has been enabled by the IPMC Note that this LED indicatesthepayloadpowerstatusbothintheearlypowerstateandthenormal blade operation OFF Payload power is d...

Page 68: ...nk Activity lower Yellow Activity Off No activity U1 U2 Blinking during BIOS Boot Blinking green to show Base interface activity Red User controlled2 U3 Blinking during BIOS Boot Green Red User controlled Turns on green following CentOS boot H S FRU State Machine During blade installation Permanently blue On board IPMC powers up Blinking blue Blade communicates with shelf manager OFF Blade is acti...

Page 69: ...E controller is routed to a front panel SFP site The ATCA 7540 provides an SFP 20 pin host connector as defined in the SFF 8431 Enhanced Small Form Factor Pluggable Module specification See the following table for the pinout Table 3 2 SFP Connector Pinout Pin Function Function Pin 1 GND GND 20 2 TX Fault Tx Data 19 3 TX Disable Tx Data 18 4 12 C SDA GND 17 5 i2 C SCL 3 3 V for Tx 16 6 Module Absen...

Page 70: ... the serial interface COM1 The on board switch 2 1 allows the swap of COM1 with COM2 making COM2 accessible through the faceplate connector instead The BIOS serial redirection feature uses COM1 as access interface Swapping the serial interfaces via SW2 1 also changes the serial connector that you need to access to make use of the serial redirection feature This will support system installations th...

Page 71: ...SATA 3 and a x4 Gen3 port to each of two M 2 sockets with Type 3 pinout and keying Each socket will support the installation of an NVMe or SATA M 2 module The modules may be Type 2280 80 mm or Type 22110 110 mm modules Table 3 3 USB Connector Pinout Pin Description 1 5 V Power 2 USB 2 0 Data 3 USB 2 0 Data 4 Power GND 5 USB 3 0 Rx Data 6 USB 3 0 Rx Data 7 Signal GND 8 USB 3 0 Tx Data 9 USB 3 0 Tx ...

Page 72: ...871A01A The location of the M 2 riser card is illustrated in the following figure The M 2 riser card board connector is a Samtec 80 pin 0 5 mm pitch ERM5 040 high speed header The pinout is provided in the following table Figure 3 4 Location of M 2 Riser Card M 2 Riser Card ...

Page 73: ...1_P PCIE_NGFF1_TX0_P 12 13 PCIE_PORT2B_RX1_N PCIE_NGFF1_TX0_N 14 15 GND GND 16 17 PCIE_PORT2B_TX2_P PCIE_PORT2B_TX1_P 18 19 PCIE_PORT2B_TX2_N PCIE_PORT2B_TX1_N 20 21 GND GND 22 23 3 3 V NGFF0_REFCLK_P 24 25 NGFF0_CLKREQ_L NGFF0_REFCLK_N 26 27 PCIE_RST_NGFF_L GND 28 29 NVME0_PEDET PCIE_NGFF0_TX0_P 30 31 SMB_NGFF_DATA PCIE_NGFF0_TX0_N 32 33 SMB_NGFF_CLK GND 34 35 NGFF0_DEVSLP PCIE_NGFF0_RX0_P 36 37 ...

Page 74: ...X2_P PCIE_PORT2A_TX2_P 54 55 PCIE_PORT2B_RX2_N PCIE_PORT2A_TX2_N 56 57 GND GND 58 59 NGFF1_DEVSLP PCIE_PORT2A_RX2_P 60 61 CLK_33K_SUSCLK PCIE_PORT2A_RX2_N 62 63 3 3 V GND 64 65 3 3 V PCIE_PORT2A_TX3_P 66 67 3 3 V PCIE_PORT2A_TX3_N 68 69 3 3 V GND 70 71 NGFF1_CLKREQ_L PCIE_PORT2A_RX3_P 72 73 NVME1_PEDET PCIE_PORT2A_RX3_N 74 75 GND GND 76 77 3 3 V 3 3 V 78 79 3 3 V 3 3 V 80 Table 3 4 M 2 Riser Card ...

Page 75: ...rs The AdvancedTCA backplane connectors reside in Zones 1 to 3 as specified by the ATCA standard and are called P10 P20 and P23 P30 P31 P32 and P3333 The pinouts of all these connectors are provided in this section Figure 3 5 Location of AdvancedTCA Connectors P31 P30 P23 P20 P32 P10 P333 ZONE 1 ZONE 2 ZONE 3 ZONE 2 ...

Page 76: ...e VM48_x_CON and RTN_x_CON Power enable ENABLE_x IPMB bus signals IPMB0_x_yyy Geographic address signals HAx Ground signals SHELF_GND and GND Reserved signals Zone 2 contains two connectors P20 and P23 They carry the following types of signals Telecom clock signals CLKx_ Base interface signals BASE_ Fabric interface signal FAB_ SAS update channel Figure 3 6 P10 Backplane Connector Pinout ...

Page 77: ...ackplane Connector Pinout Rows A to D 1 2 3 4 5 6 7 8 9 10 1 2 3 4 5 6 7 8 9 10 b c d a b c d e f g h CLK1A_P CLK1A_N CLK1B_N CLK1B_N n c n c n c n c n c n c UC_P4_TX_N UC_P2_TX_N UC_P0_TX_N n c n c n c n c n c n c UC_P4_RX_P UC_P2_RX_P UC_P0_RX_P n c n c n c n c n c n c UC_P4_RX_N UC_P2_RX_N UC_P0_RX_N n c n c n c n c n c n c UC_P4_TX_P UC_P2_TX_P UC_P0_TX_P a Figure 3 8 P20 Backplane Connector P...

Page 78: ...RD1_N n c n c n c n c FAB_CH2_RX2_P FAB_CH2_RX0_P FAB_CH1_RX2_P FAB_CH1_RX0_P BASE_CH1_TRD2_P BASE_CH2_TRD2_P n c n c n c n c FAB_CH2_RX2_N FAB_CH2_RX0_N FAB_CH1_RX2_N FAB_CH1_RX0_N BASE_CH1_TRD2_N BASE_CH2_TRD2_N n c n c n c n c Figure 3 10 P23 Backplane Connector Pinout Rows E to H 1 2 3 4 5 6 7 8 9 10 1 2 3 4 5 6 7 8 9 10 e f g h a b c d e f g h FAB_CH2_TX3_P FAB_CH2_TX1_P FAB_CH1_TX3_P FAB_CH1...

Page 79: ...n c n c PCIE_P10_RX0_N PCIE_P10_RX2_N CLK100_P10_N IPMB_SDA VP12 SAS2_RX_P SAS0_RX_P n c n c PCIE_PORT10_TX0_P PCIE_PORT10_TX2_P PCIE_RST_L V3P3_MGMT SAS2_RX_N SAS0_RX_N n c n c PCIE_PORT10_TX0_N PCIE_PORT10_TX2_N n c n c Figure 3 12 P30 Backplane Connector Pinout Rows E to H 1 2 3 4 5 6 7 8 9 10 1 2 3 4 5 6 7 8 9 10 e f g h a b c d e f g h n c SAS3_TX_P SAS1_TX_P SATA_P3_TX_P n c PCIE_P10_RX1_P P...

Page 80: ...P3_TX14_P CLK100_P3CD_P n c PCIE_P3_TX0_N PCIE_P3_TX2_N PCIE_P3_TX4_N PCIE_P3_TX6_N PCIE__P3_TX8_N PCIE_P3_TX10_N PCIE_P3_TX12_N PCIE_P3_TX14_N CLK100_P3CD _N n c Figure 3 14 P31 Backplane Connector Pinout Rows E to H PCIE_P3_RX1_N PCIE_P3_RX3_N PCIE_P3_RX5_N PCIE_P3_RX7_N PCIE_P3_RX9_N PCIE_P3_RX11_N PCIE_P3_RX13_N PCIE_P3_RX15_N PCIE_P3_RX1_P PCIE_P3_RX3_P PCIE_P3_RX5_P PCIE_P3_RX7_P PCIE_P3_RX9...

Page 81: ... n c PCIE_P9_TX0_M PCIE_P9_TX2_M PCIE_P8_TX0_M PCIE_P8_TX2_M PCIE_P7_TX0_M PCIE_P7_TX2_M PCIE_P6_TX0_M PCIE_P6_TX2_M CLK100_P8_M VP12 Figure 3 16 P32 Backplane Connector Pinout Rows E to H 1 2 3 4 5 6 7 8 9 10 1 2 3 4 5 6 7 8 9 10 e f g h a b c d e f g h PCIE_P9_RX1_P PCIE_P9_RX3_P PCIE_P8_RX1_P PCIE_P8_RX3_P PCIE_P7_RX1_P PCIE_P7_RX3_P PCIE_P6_RX1_P PCIE_P6_RX3_P CLK100_RTMPCIE7_P VP12 PCIE_P9_RX...

Page 82: ...or P333 which is used to provide additional 12 V power to RTMs With the addition of the P333 connector the ATCA 7540 can power RTMs up to 100 Watts P333 is implemented using a Tyco 120955 1 power connector The pinout is shown below Figure 3 17 P333 Connector Pin Assignment A B C D E 1 GND VP12 100 ohms to GND GND VP12 2 GND VP12 100 ohms to GND GND VP12 3 GND VP12 100 ohms to GND GND VP12 4 GND VP...

Page 83: ...ter 4 ATCA 7540 Installation and Use 6806871A01A 83 Functional Description 4 1 Block Diagram The block diagram shows how the devices work together and the data paths used Figure 4 1 ATCA 7540 Block Diagram ...

Page 84: ... have a Direct Media Interface DMI link for communication between the CPUs and the PCH The ATCA 7540 blade has one DMI link between CPU0 and the PCH It is four lane link running at PCIe 3 0 speed The DMI port on CPU1 is not used 4 3 DDR4 Main Memory The blade provides two CPUs which has six channels of independent DDR4 memory on each CPU The blade provides support for one RDIMM on each of the 12 D...

Page 85: ...s extensive I O support for the processors The PCH codename Lewisburg provides access between processors and the I O subsystem The PCH connects to CPU 0 through Intel DMI2 0 4 4 1 PCH I O Controller Features The following are the PCH I O controller features A combination of 26 configurable high speed I O ports 16 PCIe 3 0 lanes ports nine lanes used 10 USB 3 0 ports one USB 3 0 and one USB 2 0 por...

Page 86: ...igured using a 16 K byte ATC25128B SPI flash device 4 4 3 Firmware Flashes The blade has two physically separate 32 MB flash devices hosting the BIOS firmware Primary or Default BIOS Flash SPI 0 Recovery BIOS Flash SPI 1 The flash is allocated for storing the binary code of the BIOS The ATCA 7540 boots from the primary flash SPI 0 under normal circumstances If booting BIOS from primary flash SPI 0...

Page 87: ...TCA slot 4 6 1 ATCA Update Channels The Update Channel UC interface is a set of eight differential signal pairs four ports includes both Receiver and Transmitter signals that interconnect two slots These signals are used to interconnect two hub boards or redundant processor boards The slots which need to be interconnected depend on the backplane design UC Ports1 4 are connected to the Artesyn RTM ...

Page 88: ... Zone 3 SAS2 Zone 3 SAS3 MAX4952 Zone 3 SAS1 MAX4952 Zone 3 SAS2 MAX4952 Zone 3 SAS3 MAX4952 Zone 3 SAS0 ATCA 7540 ATCA 7540 E Keying E Keying Update Channel Port 0 P20 A4 D4 Update Channel Port 1 P20 E4 H4 Update Channel Port 2 P20 A3 D3 Update Channel Port 3 P20 E3 H3 Update Channel Port 4 P20 A2 D2 Node Slot Node Slot Ctrl Ctrl HDD HDD UC1 UC2 RTM RTM Front Board Front Board BackPlane Zone 2 Zo...

Page 89: ...nk including interface material guarantees a proper cooling in the system The heat sink fixture withstands shock and vibration tests 4 9 BIOS ATCA 7540providesaBIOSfirmwarethatisstoredinflashmemory Itcanbeupdatedremotely via Ethernet or locally via operating system Along with the BIOS and BIOS Setup program the flash memory contains POST and Plug and Play support The BIOS displays a message during...

Page 90: ...n ROMs temperature sensors and GPIO devices Figure 4 3 Master Only I C Bus Architecture MO I2C MicroSemi A2F200 IPMB L1 IPMB L2 AMC 1 RTM IPMB L3 AMC 2 A2F200_MO_SCL A2F200_MO_SDA ADT7461 Fortville and Board Temp Sensor 98h PCA9555 GPIO 4Ah PCA9555 GPIO 48h PCA9557 GPIO 38h AT24C512 SEL A2h AT24C512 FRU A0h FPGA FEh IPMBA IPMBB SOL_SMB LTC 4300 LTC 4300 Powerville Zone 1 CPU0 PIROM A8h CPU1 PIROM ...

Page 91: ...PROM ATCA 7540containsa64KByteSystemEventLog SEL PROM TheEEPROMhasanI Cinterface and is connected to the on board Private I C interface of IPMC building block The IDROM is assigned to I C address 0xA2 Table 4 1 IPMI I C Bus Address Map Device Name Device Type SMB Address Hex CPU0 Processor Information ROM Serial ROM A8 CPU1 Processor Information ROM Serial ROM AC FRU EEPROM 24C512 A0 SEL EEPROM 24...

Page 92: ... IPMI OEM command 4 12 Serial over LAN Serial over LAN SOL enables suitably designed blades and servers to transparently redirect a serial character stream of a baseboard UART to from a remote client via LAN over RMCP sessions This enables users at remote consoles to access the serial port of a blade server and interact with a text based BIOS console operating system command line interfaces and se...

Page 93: ...lade s faceplate reference Figure 3 1 on page 67 provides the following interfaces and control elements One SFP socket One USB 3 0 port One RJ 45 connector for RS 232 serial console One 1 GbE RJ 45 connector Recessed reset button Out of Service In Service Attention User Controlled and Hot Swap LEDs The blade design provides the possibility to cover unused faceplate elements like LEDs or push butto...

Page 94: ...1 IPMC Debug Console The IPMC Debug Console RS 232 interface connection is normally routed to a 3 pin on board header P9 The IPMC Debug monitor terminal output can also be routed to the faceplate The IPMC Debug Console is also available when the ATCA 7540 payload is powered off Table 4 2 Faceplate Serial Interfaces SW2 1 Connection HIGH Switch 2 1 OFF Default FPGA COM1 to Faceplate FPGA COM2 to RT...

Page 95: ...ontroller 4 18 Trusted Platform Module The Trusted Platform Module TPM is a specific protected and encapsulated microcontroller security chip used to defend the internal data structures against real intelligent attacks The nature of this security chip ensures that the information like keys password and digital certificates stored within are made more secure from external software attacks and physi...

Page 96: ...erfaces SMLink0B and SMLink0 4 These interfaces are intended for system management and are controlled by the Management Engine ME SMLink1 is connected to the VR13 power controllers SMLink0 and SMLink2 are connected to IPMB buses L2 and L3 Only four interfaces are used on ATCA 7540 as described in the following table The Master SMBus interface of the Lewisburg PCH is connected to on board devices l...

Page 97: ...PM 61h 53659 VDDQDEF I2C C6h PM 63h 53659 VDDQABC I2C C4h PM 62h 53622 VCCIO0 I2C ECh PM 76h 53679 VCCIN0 I2C C0h PM 60h ME_SML1_SCL ME_SML1_SDA SMB_VR_STBY_LVC3_CLK SMB_VR_STBY_LVC3_DATA Header SMB_HOST_3V3_CLK SMB_HOST_3V3_DATA RTM Payload Domain Buffer 80PCI810 Redriver B0h 80PCI810 Redriver B0h 53659 VDDQKLM I2C CAh PM 65h 53659 VDDQGHJ I2C C8h PM 64h IPMBA IPMBB SOL_SMB LTC 4300 LTC 4300 Powe...

Page 98: ... Serial EEPROM RDIMM F CPU0 memory controller 1 A8 SPD EEPROM Serial EEPROM RDIMM G CPU1 memory controller 0 A0 SPD EEPROM Serial EEPROM RDIMM H CPU1 memory controller 0 A4 SPD EEPROM Serial EEPROM RDIMM J CPU1 memory controller 0 A8 SPD EEPROM Serial EEPROM RDIMM K CPU1 memory controller 1 A0 SPD EEPROM Serial EEPROM RDIMM L CPU1 memory controller 1 A4 SPD EEPROM Serial EEPROM RDIMM M CPU1 memory...

Page 99: ...ed in Bx Dy Fz format B represents PCIe bus number value of type Hexadecimal D represents PCIe device value of type Hexadecimal F represents Function PCIe EEPROM AT24C02 ATCA 7540 PCH selected by PCA9545 A0 SFI Retimer DS110DF111 ATCA 7540 PCH enabled by PCH GPD0 30 SFI EEPROM AT24C02 ATCA 7540 PCH enabled by PCH GPD0 A8 Table 4 5 SMBus Address Map continued Device Name DeviceType Location SMBus C...

Page 100: ...ot PE1D B85 D3 F0 x4 x4 x4 x4 DMI2 B0 D0 F0 DMI2 Intel PCH Lewisburg M 2 NVMe0 B3b D0 F0 NC Fabric IF P32 P31 P30 i350 B2 D0 F0 F3 RTM ATCA 7360 L Intel 85576 B4 D0 F0 F1 LSI SAS 1064 B5e D0 F0 RTM Zone 3 Port7 Port6 RTM Zone 3 Port9 Port10 Port7 Port8 NC Not Connected PCIe Root PE1A B17 D0 F0 PCIe Uplink M 2 NVMe1 B3c D0 F0 IntelXL710 B3d D0 F0 F1 PCIe Root PE4 B0 D1c F4 PCIe Root PE8 B0 D1d F0 P...

Page 101: ... after deassertion of the reset signal reset Ext External Reset Source Default depends on external logic level Table 5 2 Register Access Type Access Description r Read only w Write only r w Read and write w1c Write 1 to clear ignore bit while reading r w1c Read and write 1 to clear write 0 has no effect r w1s Read and write 1 to set write 0 has no effect r w1t Read and write 1 to toggle write 0 ha...

Page 102: ...ation are decoded by the LPC core 5 1 1 1 2 LPC Memory Decoding The LPC interface never responds to LPC memory accesses 5 1 1 1 3 LPC Firmware Decoding The LPC interface never responds to LPC firmware accesses Table 5 3 LPC I O Register Map Overview Base Address Address Size Address Range Name Description 0x4E 2 SIW Super IO Configuration Registers for Index and Date 0x80 1 POSTCODE POST Code Regi...

Page 103: ...signal IPMC_SPI_SS_FPGA_ asserted and the SPI address 0x7F The two 7 segment LED displays are also used for power failure indication 5 1 3 Super IO Configuration Register After an LPC Reset PCH_PLTRST_ is asserted or Power On Reset the Super IO is in the Run Mode with the UARTs disabled They may be configured using the LPC I O Address Range INDEX and DATA by placing the Super IO into Configuration...

Page 104: ...the Configuration State The device exits the Configuration State by the following contiguous sequence 1 Write 68H to Configuration Index Port 2 Write 08H to Configuration Index Port 5 1 3 3 Configuration Mode The system sets the logical device information and activates desired logical devices through the INDEX and DATA ports The desired configuration registers are accessed in two steps 1 Write the...

Page 105: ...e ADDRESS port are used for register selection All unimplemented registers and bits ignore writes and return zero when read The INDEX PORT is used to select a configuration register in the chip The DATA PORT is then used to access the selected register These registers are accessible only in the Configuration Mode NOTICE If accessing the Global Configuration Registers Step 1 is not required The Sup...

Page 106: ...O Device Identification Register Index Address 0x20 Bit Description Default Access 7 0 Device ID 0x0 LPC r Table 5 11 Super IO Device Revision Register Index Address 0x21 Bit Description Default Access 7 0 Device Revision 0x01 LPC r Table 5 12 Super IO LPC Control Register Index Address 0x28 Bit Description Default Access 0 LPC Bus Wait States 1 Long wait states sync 6 1 LPC r 7 1 Reserved 0 LPC r...

Page 107: ... to select a specific logical device register These registers are then accessed through the DATA PORT The Logical Device registers are accessible only when the device is in the Configuration state 1 SERIRQ Mode 1 Continuous Mode 1 LPC r 3 2 UART Clock pre divide 00 divide by 1 01 divide by 8 10 divide by 26 CLK_UART is 48 MHz 11 reserved 0 LPC r w 7 4 Reserved 0 LPC r Table 5 13 Global Super IO SE...

Page 108: ...gical Device Enable 0 disabled Currently selected device is inactive 1 enabled The currently selected device is enabled 1 LPC r w 7 1 Reserved 0 LPC r Table 5 16 Logical Device Base I O Address MSB Register Index Address 0x60 Bit Description Default Access 7 0 Logical Device Base I O Address MSB 0 LPC r w Table 5 17 Logical Device Base I O Address LSB Register Index Address 0x61 Bit Description De...

Page 109: ...13 0xE IRQ14 0xF IRQ15 0 LPC r w 7 4 Reserved 0 LPC r NOTICE An Interrupt is activated by enabling this device offset 0x30 setting this register to a non zero value and setting any combination of bits 0 4 in the corresponding UART IER and the occurrence of the corresponding UART event i e Modem Status Change Receiver Line Error Condition Transmit Data Request Receiver Data Available or Receiver Ti...

Page 110: ...ion of certain ofthe UART registers The DLAB bit must be set high by the system software to access the Baud Rate Generator Divisor Latches DLL and DLM Table 5 21 Logical Device 0x75 Reserved Register Index Address 0x75 Bit Description Default Access 7 0 Reserved 0x04 LPC r Table 5 22 Logical Device 0xF0 Reserved Register Index Address 0xF0 Bit Description Default Access 7 0 Reserved 0 LPC r Table ...

Page 111: ...r holds the next data byte to be transmitted When the Transmit Shift Register becomes empty the contents of the Transmit Holding Register are loaded into the shift register and the transmit data request TDRQ bit in the Line Status Register is set to one Base 4 X Modem Control Register MCR Base 5 X Line Status Register LSR Read Only Base 6 X Modem Status Register MSR Read Only Base 7 X Scratch Regi...

Page 112: ...imilarly by setting the appropriate bits selected interrupts can be enabled Table 5 26 Interrupt Enable Register IER if DLAB 0 LPC I O Address Base 1 Bit Description Default Access 0 Receive data interrupt enable disable 1 receive data interrupt enabled 0 receive data interrupt disabled 0 LPC r w 1 Transmitter holding register empty THRE interrupt enable disable 1 THRE interrupt enabled 0 THRE int...

Page 113: ...in non FIFO mode RBR has data 2 Receiver Time out occurred It happens in FIFO mode only when there is data in the receive FIFO but no activity for a time period 3 Transmitter requests data In FIFO mode the transmit FIFO is half or more than half empty in non FIFO mode THR is read already 4 Modem Status one or more of the modem input signals has changed state Table 5 28 Interrupt Identification Reg...

Page 114: ...de Trigger level was reached FIFO mode Reading bytes until Receiver FIFO drops below trigger level or setting RESETRF bit in FCR register 0b1100 Character Timeout indication FIFO Mode only At least 1 character is in receiver FIFO and there was no activity for a time period Reading the Receiver FIFO or setting RESETRF bit in FCR register 0b0010 3 Transmit FIFO Data Request Non FIFO mode Transmit Ho...

Page 115: ...de continued Interrupt ID Interrupt Set Reset Function 3 0 Priority Type Source Reset Control Table 5 30 FIFO Control Register FCR LPC I O Address Base 2 Bit Description Default Access 0 FIFO enable disable 1 Transmitter and Receiver FIFO enabled 0 FIFO disabled 0 LPC w 1 Receiver FIFO reset 1 Bytes in receiver FIFO and counter are reset Shift register is not reset bit is self clearing 0 No effect...

Page 116: ... LCR LPC I O Address Base 3 Bit Description Default Access 1 0 Serial character WORD length 00 5 bits 01 6 bits 10 7 bits 11 8 bits 0 LPC r w 2 Stop bit length 1 1 5 stop bits for 5 bit WORD length 1 2 stop bits for 6 7 and 8 bit WORD length 0 1 stop bit for any serial character WORD length 0 LPC r w 3 Parity enable disable When bit3isset aparitybitisgeneratedintransmitted data between the last da...

Page 117: ... disabled 0 LPC r w 6 Break control bit Bit 6 is set to force a break condition i e a condition where TXD is forced to the spacing cleared state When bit 6 is cleared the break condition is disabled andhasnoaffectonthetransmitterlogic Itonlyeffects TXD 1 Break condition enabled 0 Break condition disabled 0 LPC r w 7 Divisor latch access bit DLAB Bit 7 must be set to access the divisor latches of t...

Page 118: ...ntrol signal OUT2 1 OUT2 output in high state 0 OUT2 output in low state Not supported 0 LPC r w 4 Local loop back diagnostic control When loop back is activated Transmitter TXD is set high Receiver RXD is disconnected Output of Transmitter Shift register is looped back into the receiver shift register input Modem control inputs are disconnected Modem control outputs are internally connected to mo...

Page 119: ...n the FIFO is read and a new character is now at the top of the FIFO Bitsone throughfouraretheerror conditionsthatproduce areceiverlinestatus interrupt when any of the corresponding conditions are detected and the interrupt is enabled These bits are not cleared byreadingthe erroneousbytefrom the FIFOorreceive buffer Theyarecleared only by reading LSR In FIFO mode the line status interrupt occurs o...

Page 120: ... selected in the LCR bit4 PEisclearedeverytimetheCPUreadsthecontentsof the LSR In the FIFO mode this error is associated with the particular character in the FIFO to which it applies This error is revealed to the CPU when its associated character is at the top of the FIFO 1 Parity error occurred 0 No parity error 0 LPC r 3 Framing Error FE indicator When FE is set it indicates that the received ch...

Page 121: ...ceeded 0 Normal operation 0 LPC r 5 Transmit Holding Register Empty THRE indicator THRE is set when the THR is empty indicating that the ACE is ready to accept a new character If the THRE interrupt is enabled when THRE is set an interrupt is generated THRE is set when the contents of the THR are transferred to the TSR THRE is cleared concurrent with the loading of the THR by the CPU In the FIFO mo...

Page 122: ...there is at least one parity framing or break error in the FIFO It is cleared when the microprocessor reads the LSR and there are no subsequent errors in the FIFO If FIFO is not used bit always reads 0 1 FIFO data error encountered 0 No FIFO error encountered 0 LPC r Table 5 33 Line Status Register LSR continued LPC I O Address Base 5 Bit Description Default Access Table 5 34 Modem Status Register...

Page 123: ...chiphaschanged state since the last time it was read by the CPU When DDCD is set and the modem status interrupt is enabled a modem status interrupt is generated Not supported 0 LPC r w 4 Complement of the clear to send CTS input When the Asynchronous Communications Element ACE is in diagnostic test mode LOOP MCR4 1 this bit is equal to the MCR bit 1 Ext LPC r 5 Complement of the data set ready DSR...

Page 124: ...re loaded with 0 the 16X output clock is stopped Upon loading either of the divisor latches a 16 bit baud counter is immediately loaded This prevents long counts on initial load Accessto the divisor latch can be done with a word write The UART_CLK is the CLK_UART 48 MHz input divided by the pre divider set by the Super IO Configuration Register Offset 0x29 The baud rate of the data shifted in out ...

Page 125: ...e address An LPC I O write access to an address not listed in this table or marked with an in the LPC I O column is ignored A corresponding read access delivers always zero used and reserved for future extensions A reserved register is read only and deliver always zero Areserved bit is read only and always reads zero Table 5 36 Divisor Latch LSB Register DLL if DLAB 1 PC I O Address Base Bit Descr...

Page 126: ...w r Serial Redirection Control Register See Table 5 41 0x04 r r w Serial over LAN Control Register See Table 5 42 0x05 r r w Serial Line Routing Register See Table 5 43 0x06 r r w IPMC Power Level Register 0x07 r r w IPMC Power Level Multiplier Register 0x08 r ME Power Failure State Register See Table 5 44 0x09 r ME Power Failure Cause Register See Table 5 46 0x0A r Payload Power Failure State Reg...

Page 127: ...ntrol Register See Table 5 70 0x24 r External Interrupt Status Register See Table 5 71 0x25 0x27 r w Interrupt Mask and Map Registers on page 151 0x30 0x37 r w r w CPU0 Hot Plug I C I O Expander Registers on page 153 0x38 0x3F r w r w CPU1 Hot Plug I C I O Expander Registers on page 153 0x40 r r w Flash Status Register See Table 5 77 0x41 r w r PCH Output Enable Register See Table 5 78 0x42 r w RT...

Page 128: ...e Table 5 95 0x66 0x67 r w Telecom Clock Monitor Frequency Period Register See Table 5 96 0x68 0x69 r w Telecom Clock Monitor Lower Limit Register See Table 5 97 0x6A 0x6B r w Telecom Clock Monitor Upper Limit Register See Table 5 98 0x74 r w r BIOS Version Register 1 See Table 5 99 0x75 r w r BIOS Version Register 2 See Table 5 100 0x76 r w r BIOS Version Register 3 See Table 5 101 0x78 r r w IPM...

Page 129: ...The IPMC uses this information to route the corresponding port to serial IPMC interface in case of SOL Table 5 39 Module Identification Register Address Offset 0x00 Bit Description Default Access 15 0 ATCA 7540 Blade Module Identification 0x7540 r Table 5 40 FPGA Version Register Address Offset 0x02 Bit Description Default Access 7 0 Specifies FPGA version 0x1 Initial Value r NOTICE BIOS should ne...

Page 130: ...edirection Control Register continued Address Offset 0x03 Bit Description Default Access NOTICE When both control bits are enabled bit 1 is ignored Serial over LAN is done through NCSI from IPMC MAC to PCH Therefore this register is implemented as backup option Table 5 42 Serial over LAN Control Register Address Offset 0x04 Bit Description Default Access 0 SOL over COM1 enable 0 disabled 1 enabled...

Page 131: ...RIAL which is controlled by switch SW2 1 0 COM1 to Faceplate and COM2 to RTM 1 COM1 to RTM and COM2 to Faceplate Note Setting may be overwritten by IPMC Software controlling Bit 4 Ext SW2 1 0 OFF 1 ON r 1 Inverted level of signal IPMC_SER_2_HEADER which is controlled by switch SW2 2 0 IPMC Serial Debug Interface to 3 Pin Header 1 IPMC Serial Debug Interface to Faceplate Note Setting may be overwri...

Page 132: ...0 ME Power Failure State Latched last ME state when failure occurred See Table 5 48 ME Power Failure States Note Only valid with ME Failure Bit 7 set PWR_GOOD 0 IPMC r 6 3 Reserved 0 IPMC r 7 ME Failure ME state machine sampled a failing ME Power status 0 No ME Failure Normal ME operation 1 ME failure ME failure detected PWR_GOOD 0 IPMC r Table 5 45 ME Power Failure States State Coding State Name ...

Page 133: ...t Access 0 Active Sleep Well ASW power failure 0 No ASW power failure ASW power is as expected 1 ASW power failure ASW power has different value as expected Note Only valid when ME Failure Bit 7 of ME Power Failure State Register Table 5 47 is set PWR_GOOD 0 IPMC r 7 1 Reserved 0 IPMC r Table 5 47 Payload Power Failure State Register Address Offset 0x0A Bit Description Default Access 4 0 PayloadPo...

Page 134: ...ebug disabled after 280 ms Tracked voltages are not good Other cause 12 V or 5 V aux power failure 0x8 VCCIN_ENABLE Timeout debug disabled after 280 ms VCCIN voltages are not good Other cause One or more voltages have failed which have been already enabled and sampled good 0x9 VCCIO_VPP_ENA BLE Timeout debug disabled after 280 ms VCCIO and VPP voltages are not good Other cause One or more voltages...

Page 135: ...ption Table 5 49 Payload Power Failure Cause Register 1 Address Offset 0x0B Bit Description Default Access 0 Payload wakeup failure 0 No wakeup issue Blade wakes up within 5s timeout 1 Wakeup failure Blade does not wake up SLP_S3_ stays low within 5s timeout PWR_GOOD 0 IPMC r 1 VCCIO power good failure signal PWRGD_PVCCIO 0 No VCCIO power issue 1 VCCIO power failure PWR_GOOD 0 IPMC r 6 2 Reserved ...

Page 136: ...0 V power good failure signal PWRGD_V1P0 0 No 1 0 V power issue 1 1 0 V power failure PWR_GOOD 0 IPMC r 4 0 75 V power good failure signal PWRGD_V0P75 0 No 0 75 V power issue 1 0 75 V power failure PWR_GOOD 0 IPMC r 5 3 3 V and 1 05 V power good failure signal PWRGD_V3P3_V1P05 0 No 3 3 V and 1 05 power issue 1 3 3 V and 1 05 power failure PWR_GOOD 0 IPMC r 6 1 8 V power good failure signal PWRGD_V...

Page 137: ... power issue 1 VDD CPU0 power failure PWR_GOOD 0 IPMC r 3 VDD CPU1 power good failure signal PWRGD_VDD_EFGH 0 No VDD CPU1 power issue 1 VDD CPU1 power failure PWR_GOOD 0 IPMC r 4 VTT CPU0 power good failure signal PWRGD_VTT_ABCD 0 No VTT CPU0 power issue 1 VTT CPU0 power failure PWR_GOOD 0 IPMC r 5 VTT CPU1 power good failure signal PWRGD_VTT_EFGH 0 No VTT CPU1 power issue 1 VTT CPU1 power failur ...

Page 138: ...rom different sources without clearing the corresponding register bits one cannot determine the most recent reset source since more than one bit will be set The same situation will happen if two reset sources go active at the same time Table 5 52 Power Status Register Address Offset 0x0E Bit Description Default Access 0 Status of signal SLP_A_ Ext IPMC r 1 Status of signal SLP_S4_ Ext IPMC r 2 Sta...

Page 139: ...d Table 5 53 BIOS Reset Source Register Address Offset 0x10 Bit Description Default Access 0 PWR_GOOD Payload Power on reset 1 Reset occurred PWR_GOOD 1 LPC r w1c IPMC r 1 XDPx reset request Any one of XDPx signal caused reset 1 Reset occurred PWR_GOOD 0 LPC r w1c IPMC r 2 PB_RST_ face plate push button reset 1 Reset occurred PWR_GOOD 0 LPC r w1c IPMC r 3 Reserved 0 r 4 RTM_PB_RST_ Reset key at RT...

Page 140: ...F 0 SW2 4 is ON LPC r w 3 Reserved 0 r 4 RTM_PB_RST_ Reset key at RTM 1 enabled 0 disabled Ext FACE_PB_EN 1 SW2 4 is OFF 0 SW2 4 is ON LCP r w 7 5 Reserved 0 r Table 5 54 Reset Mask Register continued Address Offset 0x11 Bit Description Default Access NOTICE The OS should never write to this register Table 5 55 BIOS IPMC Watchdog Timeout Register Address Offset 0x12 Bit Description Default Access ...

Page 141: ...er bits one cannot determine the most recent reset source since more than one bit will be set The same will happen if two reset sources go active at the same time NOTICE After a timeout of 8s the resets are armed again Table 5 56 BIOS Push Button Enable Register Address Offset 0x13 Bit Description Default Access 7 0 BIOS Push Button Enable Register LPC w NOTICE The BIOS should never write to this ...

Page 142: ...5 Reserved 0 r 6 PCH_PLTRST_ reset 1 Reset occurred PWR_GOOD 0 LPC r w1c IPMC r 7 IPMC_RST_ REQ_ Payload Reset from IPMC 1 Reset occurred PWR_GOOD 0 LPC r w1c IPMC r Table 5 57 OS Reset Source Register continued Address Offset 0x14 Bit Description Default Access NOTICE The BIOS should never write to this register Table 5 58 OS IPMC Watchdog Timeout Register Address Offset 0x15 Bit Description Defa...

Page 143: ... corresponding register bits one cannot determine the most recent reset source since more than one bit will be set The same situation will happen if two reset sources go active at the same time NOTICE The IPMC needs to clear the IPMC watchdog timeout bit to arm IPMC watchdog timeout event recognition Table 5 59 IPMC Watchdog Timeout Register Address Offset 0x16 Bit Description Default Access 0 IPM...

Page 144: ...Reset occurred PWR_GOOD 0 IPMC r w1c 5 Reserved 0 r 6 PCH_PLTRST_ reset 1 Reset occurred PWR_GOOD 0 IPMC r w1c 7 IPMC_RST_ REQ_ Payload Reset from IPMC 1 Reset occurred PWR_GOOD 0 IPMC r w1c Table 5 60 IPMC Reset Source Register continued Address Offset 0x17 Bit Description Default Access NOTICE IPMC version 1 2 0018 or higher is needed to clear the interrupt flag Otherwise the IPMC interrupt will...

Page 145: ...H_ADR_IRQ_ signal is asserted When PCH signals completion with assertion of ADR_COMPLETE the Reset State Machine asserts PCH_SYS_RST_ If ADR is not enabled PCH_SYS_RST_ is generated immediately without the assertion of PCH_ADR_IRQ_ signal Table 5 62 DIMM ADR Feature Configuration Register Address Offset 0x18 Bit Description Default Access 0 ADR enable for Push button reset 1 ADR enabled 0 ADR disa...

Page 146: ...ol Register information Table 5 63 DIMM ADR Status Register Address Offset 0x1A Bit Description Default Access 0 Indicates if the ADR feature is enabled GPIO37 of Cavecreek 0 ADR disabled PCH_ADR_IRQ_ is driven high 1 ADR enabled PCH_ADR_IRQ_ is driven low PWR_GOOD 0 LPC r w1c IPMC r 7 1 Reserved 0 r Table 5 64 CPU Control Register Address Offset 0x1E Bit Description Default Access 0 PCH_PSTATE_ p...

Page 147: ...gisters IPMC can initiate a NMI Host can identify NMI comes from IPMC Table 5 65 S States Control Register Address Offset 0x1F Bit Description Default Access 0 SCI pulse generation Minimum low pulse width is 45 ms 0 No action 1 Generate SCI low pulse Trigger S0 S3 transition IPMC w 1 PWRBTN pulse generation Minimum low pulse width is 32 ms 0 No action 1 Generate PWRBTN low pulse Trigger S3 S5 S0 t...

Page 148: ... pulse the host can identify this event reading the register below The host needs to clear this flag Table 5 66 NMI Generation Register Address Offset 0x20 Bit Description Default Access 7 0 NMI pulse generation Minimum pulse width is 175 μs 0xA5 Generate NMI pulse All other values are ignored IPMC w Table 5 67 NMI Status Register Address Offset 0x20 Bit Signal Group Description Default Access 0 P...

Page 149: ...Telecom interrupt sources need to be enabled Use of this register is optional the same information can be found in Table 5 92 and Table 5 93 These tables also show how to clear the corresponding interrupt status bits Table 5 68 Internal Interrupt Status Register Address Offset 0x21 Bit Description Default Access 0 IPMC signals interrupt Host clears flag 0 LPC r 1wc IPMC generates host interrupt 0 ...

Page 150: ... Offset 0x23 Bit Description Default Access 3 0 Telecom CLK_MONITOR_FINISHED interrupt enable Enable Disable interrupt for the corresponding Clock source 0 interrupt is disabled 1 Interrupt is enabled 0 LPC r w 7 4 Telecom CLK_MONITOR_OUT_OF_RANGE interrupt Enable Disable interrupt for the corresponding Clock source 0 interrupt is disabled 1 Interrupt is enabled 0 LPC r w Table 5 71 External Inter...

Page 151: ...MultipleinterruptsourcesmaysharethesameIRQFrame Inthiscaseallinterruptsourcesneed to be of type level active low Each interrupt source has an Interrupt Mask and Map Register See the following table for details Table 5 72 Address Map of Interrupt Mask and Map Registers Interrupt Source s Description AddressOffset of Interrupt Mask IPMC to Host Interrupt IPMC signals interrupt 0x25 Telecom Interrupt...

Page 152: ... number 2 IRQ1 0x03 Frame number 3 IRQ2 SMI_ 0x04 Frame number 4 IRQ3 0x05 Frame number 5 IRQ4 0x06 Frame number 6 IRQ5 0x07 Frame number 7 IRQ6 0x08 Frame number 8 IRQ7 0x09 Frame number 9 IRQ8 0x0A Frame number 10 IRQ9 0x0B Frame number 11 IRQ1 0x0C Frame number 12 IRQ11 0x0D Frame number 13 IRQ12 0x0E Frame number 14 IRQ13 0x0F Frame number 15 IRQ14 0x10 Frame number 16 IRQ15 0x11 Frame number ...

Page 153: ...5 74 Hot Plug Virtual Pin Port Register Address Offset CPU0 Port 1 0x30 Port 2 0x31 Port 3 0x32 Port 4 0x33 CPU1 Port 1 0x38 Port 2 0x39 Port 3 0x3A Port 4 0x3B Bit Signal Name Direction Description Default Access 0 ATNLED Output This indicator is connected to the Attention LED on the baseboard For a precise definition refer to PCI Express Base Specification Revision 3 0 Ext r 1 PWRLED Output This...

Page 154: ...ly Electromechanical latch is used to electro mechanically hold the card in place and is operated by software MRL is used for card edge and EMLSTS is used for SIOM form factors 1 IPMC r w LPC r 7 EMIL Output Electromechanical retention latch control output that opens or closes the retention latch on the blade for this slot A retention latch is used on the platform to mechanically hold the cardin p...

Page 155: ...ts TARGET_BOOT_SELECT and CURRENT_BOOT_SELECT are different an alternate BIOS needs to be selected In this case the platform reset will be transformed by the FPGA logic to payload power cycle including the ME This is done to guarantee no SPI access to boot flash when switching the other device Table 5 75 Address Control for PCA9555 Internal Register Address Offset CPU0 Device1 Slave address 0x20 0...

Page 156: ... 1 SW1 3 ON r 5 Manual Boot Flash select enable Signal BOOT_SEL_EN_ 0 Signal BOOT_SELECT selects active Boot Flash 1 Switch SW3 2 selects the active Boot Flash Ext 0 SW3 1 OFF 1 SW3 1 ON r 6 Manual Boot Flash select Signal BOOT_DEFAULT Used when SW3 1 is ON 0 Selects Default Boot SPI Flash 1 Selects Recover Boot SPI Flash Ext 0 SW3 2 OFF 1 SW3 2 ON r 7 TARGET_BOOT_SELECT Target Boot Flash Selectio...

Page 157: ... RTM_SPI_SCK RTM_SPI_SS_ RTM_SPI_MISO and RTM_SPI_MOSI are used to support a SPI master protocol The signal RTM_SPI_MISO is also used to signal an RTM interrupt to the baseboard See Flash Status and Selection Registers on page 155 Table 5 78 PCH Output Enable Register Address Offset 0x41 Bit Description Default Access 0 PCH_RCIN_ enable 0 Disabled Signal is tri state 1 Enabled Drive pch_rcin 0 LPC...

Page 158: ... the SPI device A write access to the RTM SPI Address Command Register with the Command Bit 1 Read starts a SPI read transaction This contains the data read from the SPI device Table 5 79 RTM SPI Address Command Register Address Offset 0x42 Bit Description Default Access 0 Command Bit 0 Write 1 Read 0 LPC r w 7 1 RTM SPI Address bits 6 0 0 LPC r w Table 5 80 RTM SPI Write Register Address Offset 0...

Page 159: ...driven low 1 UC1_EQ_TX is tri state 0 LPC r w IPMC r 2 Control output Signal UC2_EQ_RX 0 UC2_EQ_RX is driven low 1 UC2_EQ_RX is tri state 0 LPC r w IPMC r 3 Control output Signal UC2_EQ_TX 0 UC2_EQ_TX is driven low 1 UC2_EQ_TX is tri state 0 LPC r w IPMC r 4 Control output Signal UC3_EQ_RX 0 UC3_EQ_RX is driven low 1 UC3_EQ_RX is tri state 0 LPC r w IPMC r 5 Control output Signal UC3_EQ_TX 0 UC3_E...

Page 160: ...LPC r w IPMC r 7 2 Reserved 0 r Table 5 84 RTM Status Register Address Offset 0x4B Bit Description Default Access 0 RTM power good status 0 RTM power not stable or RTM not powered 1 RTM power good Ext RTM_PWRGD IPCM r 7 1 Reserved 0 IPCM r Table 5 85 RTM Interrupt Status Register Address Offset 0x4C Bit Description Default Access 0 Faceplate Ethernet 1 Interrupt signal PV_FPETH_1_INT_ 0 No interru...

Page 161: ... is driven low LED on 0 r w 1 Control read LED output Signal LED_RED_ 0 LED_RED_ is driven high LED off 1 LED_RED_ is driven low LED on 0 r w 2 Control user LED output Signal LED_USER1_ 0 LED_USER1_ is driven high LED off 1 LED_USER1 is driven low LED on 0 r w 3 Control user LED output Signal LED_USER2_ 00 LED_USER2_ is driven high LED off 01 LED_USER2 is driven low LED on 0 r w 7 4 Reserved 0 r T...

Page 162: ... Presence Detection Status of signal CPU0_SKTOCC_ 0 CPU present in socket 1 CPU not present Socket is empty Ext r 3 CPU1 Presence Detection Status of signal CPU1_SKTOCC_ 0 CPU present in socket 1 CPU not present Socket is empty Ext r 7 4 Reserved 0 r Table 5 89 CPU Error Status Register Address Offset 0x57 Bit Signal Description Default Access 0 CPU_ERR_ 0 CPU Error status signals Bit 0 Non critic...

Page 163: ...st Number Name Description 0 SYSCLK_IN_CLK1A CLK1A from backplane 1 SYSCLK_IN_CLK1B CLK1B from backplane 2 SYSCLK_IN_CLK2A CLK2A from backplane 3 SYSCLK_IN_CLK2B CLK2B from backplane Table 5 91 Telecom Clock Monitor Control Register Address 0x60 Bit Description Default Access 3 0 Enable supervised Telecom Clock 0 to 3 Set corresponding bit enable monitoring 0 LPC r w 7 4 Reserved 0 r Table 5 92 Te...

Page 164: ...ode Corresponding bit is set when the number of positive Clock edges within the selected time base is Lower limit or Upper limit Period Mode Corresponding bit is set when the Clock 0 Period within the selected time base is Lower limit or Upper limit Clearing bit triggers new sequence of measurements 0 LPC r w1c 7 4 Reserved 0 r Table 5 94 Telecom Clock Monitor Select Register Address 0x63 Bit Desc...

Page 165: ...13 Gate is open for 2048 ms 14 Gate is open for 4096 ms 15 Gate is open for 8192 ms 16 Gate is open for 16384 ms 17 and all others Gate is open for 32768 ms 0 LPC r w Select Time base for clock supervision with Period Mode 0 Period Counter incremented with each master clock 1 Period Counter incremented with each 2nd master clock 2 Period Counter incremented with each 4th master clock 3 Period Coun...

Page 166: ...ase 1 65534 Number of clocks during one supervised clock period 65535 Overflow Supervised clock to slow for time base Note Only valid when corresponding bit in Table 5 92 Telecom Clock Monitor Status Register is set 0 LPC r Table 5 97 Telecom Clock Monitor Lower Limit Register Address 0x67 0x68 Bit Description Default Access 15 0 Lower Limit for supervised Telecom Clock Used by Table 5 93 Telecom ...

Page 167: ...dress Offset 0x74 Bit Description Default Access 7 0 BIOS Version bits 0 to 7 0 LPC r w IPMC r Table 5 100 BIOS Version Register 2 Address Offset 0x75 Bit Description Default Access 7 0 BIOS Version bits 8 to 15 0 LPC r w IPMC r Table 5 101 BIOS Version Register 3 Address Offset 0x76 Bit Description Default Access 7 0 BIOS Version bits 16 to 23 0 LPC r w IPMC r Table 5 102 IPMC BIOS Communication ...

Page 168: ...ommunication bits PWR_GOOD 0 LPC r w IPMC r w Table 5 104 IPMC BIOS Communication Register 3 Address Offset 0x7C Bit Description Default Access 7 0 IPMC BIOS Communication bits PWR_GOOD 0 LPC r w IPMC r w Table 5 105 LPC Scratch Register Address Offset 0x7D Bit Description Default Access 7 0 LPC Scratch bits PWR_GOOD 0 LPC r w IPMC r Table 5 106 IPMC Scratch Register Address Offset 0x7E Bit Descri...

Page 169: ...meter 96 on page 234 The BIOS used on the blade is based on the Insyde UEFI BIOS with several Artesyn extensions integrated Its main features are Initialize CPU chipset and memory Initialize PCI devices Setup utility for setting configuration data IPMC support Serial console redirection for remote blade access Boot operation system The BIOS complies with the following specifications UEFI Specifica...

Page 170: ... for Serial Console Redirection For serial console redirection the following are required Terminal or terminal emulation which supports a VT100 mode NULL modem cable Terminal emulation programs such as TeraTermPro or Putty can be used 6 2 2 Default Access Parameters By default the blade is accessed using the serial interface COM1 By default this interface is accessible using an RJ 45 connector at ...

Page 171: ...al console redirect feature 1 Configure terminal to communicate using the same parameters as in BIOS setup 2 Connect the terminal to NULL modem cable 3 Connect the NULL modem cable to COM port of the blade 4 Start up the blade 6 3 Changing Configuration Settings When the system is switched on or rebooted the presence and functionality of the system components is tested by Power On Self Test POST ...

Page 172: ...es are shown at the bottom of the menu Additionally an item specific help is displayed on the right side of the window Figure 6 1 Main Menu Make sure BIOS is properly configured prior to installing the operating system and its drivers If you save changes in setup the next time the blade boots up BIOS configures the system according to the setup selections stored If those values cause the system bo...

Page 173: ...ystem which contains the OS loader During the POST procedure the UEFI BIOS scans all storage devices that are connected to the system for a valid GUID Partition Table GPT If there is a known boot loader found in the EFI System Partition a new entry is added to the boot order list For example if the EFI System Partition contains the EFI redhat grub efi file BIOS will add Red Hat Linux to the boot l...

Page 174: ...t UEFI Boot Type Only UEFI boot devices OS loader are in the boot order list 6 4 3 Supported Boot Devices The BIOS supports booting from the following devices sources NVMe disk connected to the NVMe interface available only when NVMe SSD is assembled Solid State Disk connected to the SATA interface available only when SSD SATA is assembled USB devices floppy CD ROM and hard disk PXE boot from Fron...

Page 175: ...thedevicesfromwhichBIOSattemptstoboottheoperatingsystem By Boot Menu 1 Press F4 key to enter the Boot menu 2 Enter Boot Manager 3 Override existing boot sequence by selecting another boot device from the boot list Figure 6 2 Boot Device Priority If the BIOS is not successful at booting from one device it tries to boot from the next device on the list When the BIOS does not find any bootable device...

Page 176: ... Installation and Use 6806871A01A Figure 6 3 Boot Menu If a selected legacy boot device does not load the operating system BIOS will reset the blade If an EFI boot device does not load the operating system it will return to the Boot Manager ...

Page 177: ...hat in the BIOS Setup in the Boot Menu the Boot Type is set to Dual Boot Type or UEFI Boot Type and the PXE Boot capability is set to UEFI IPv4 Steps to configure iSCSI boot 1 Enter the Boot Menu Front Page by pressing the F4 key 2 Select Device Manager from the Boot Menu 3 Select the iSCSI Configuration Menu 4 Enter an iSCSI Initiator Name 5 Add one or more iSCSI Attempts 6 Save the iSCSI configu...

Page 178: ...u Item Values IPMI Boot Parameter Description ISCSI Initiator Name The worldwide unique name of the iSCSI Initiator Only IQN format is accepted Add Attempt Add an iSCSI Attempt Delete Attempts Delete an iSCSI Attempt Change Attempt Order Change the order of iSCSI Attempts Figure 6 5 Attempt Configuration 1 ...

Page 179: ...your target is also configured for MPIO Internet Protocol IP4 IP6 Autoconfigure Can be set to IP4 IP6 or Autoconfigure In Autoconfigure mode the iSCSI driver attempts to connect to the iSCSI target using the IPv4 stack If this fails then the iSCSI driver attempts to connect using the IPv6 stack Connection Retry Count The count range is 0 to 16 If set to 0 there are no retries 0 40 The minimum valu...

Page 180: ...tted decimal notation Gateway Use to set initiator gateway IP address in dotted decimal notation Target Name The worldwide unique name of the target Only IQN format is accepted Target IP address Use to set target IP address in dotted decimal notation Target Port Use to change target port number Default is 3260 Boot LUN Use to set the hexadecimal representation of the boot logical unit number LUN E...

Page 181: ...n page 235 The main advantage of using IPMI boot parameter is that the parameters stored as IPMI boot parameters are not changed after a BIOS upgrade or a BIOS boot bank switch BIOS will not return to the BIOS default settings after a BIOS upgrade Normally the BIOS setup parameters are stored within the BIOS flash The following figure and description helps you to understand how a BIOS setup parame...

Page 182: ...tings 1 User enters the BIOS setup and changes some parameters 2 User selects Save or Save and Exit option 3 BIOS writes the parameter to the BIOS Parameter in the Flash 4 BIOS writes the parameter to the IPMI Boot Parameter USER area Load Defaults 1 User enters BIOS setup and selects Load Defaults 2 BIOS reads Default Parameter from Flash into the Setup Figure 6 7 IPMI Boot Parameter BIOS Paramet...

Page 183: ...ter to the BIOS Parameter in the Flash 6 BIOS writes the parameter to the IPMI Boot Parameter USER area 6 7 BIOS Setup Configuration This section provides information about the various configurations in the BIOS setup menu NOTE The following command can be used to read the IPMI boot parameters default area ipmibpar b 6 7 1 Main The figure below shows the Main menu options Figure 6 8 Main Menu Opti...

Page 184: ...in menu options 6 7 2 Advanced This figure below shows the Advanced menu options Table 6 3 Main Menu Item Values IPMI Boot Parameter Description System Time 15 48 21 Set the Time Use Enter to switch between Time elements System Date Thu 11 11 2014 Set the Date Use Enter to switch between Date elements Figure 6 9 Advanced Menu ...

Page 185: ...Basic Input Output System ATCA 7540 Installation and Use 6806871A01A 185 6 7 2 1 Platform Information This option shows important Platform Information Figure 6 10 Platform Information ...

Page 186: ...MI Boot Parameter Description Auto Detect RTM Enabled Disabled rtm_auto Ifenabled theRTMisdetectedandtheRTM PCI Express parameter are set for this RTM If disabled the RTM PCI Express parameter can be set manually CPU0 PCIe to RTM Width X4x4x4x4 x4x4x8 x8x4x4 x8x8 rtm_cpu0_bif SelectsCPU0PCIeBifurcationforZone3 connector RTM CPU0 PCIe Port 3A Auto Gen 1 2 5 GT s Gen 2 5 GT s Gen 3 8 GT s rtm_cpu0_3...

Page 187: ... Speed for Zone 3 connector RTM CPU1 PCIe to RTM Width X4x4x4x4 x4x4x8 x8x4x4 x8x8 rtm_cpu1_bif Selects CPU1 PCIe Bifurcation for Zone 3 connector RTM CPU1 PCIe Port 3A Auto Gen 1 2 5 GT s Gen 2 5 GT s Gen 3 8 GT s rtm_cpu1_3a Selects CPU1 PCIe Port 3A Speed for Zone 3 connector RTM CPU1 PCIe Port 3B Auto Gen 1 2 5 GT s Gen 2 5 GT s Gen 3 8 GT s rtm_cpu1_3b Selects CPU1 PCIe Port 3B Speed for Zone...

Page 188: ...lects CPU1PCIePort 3D Speed for Zone 3 connector RTM Figure 6 12 Peripheral Configuration Table 6 4 Advanced RTM Configuration continued Item Values IPMI Boot Parameter Description Table 6 5 Advanced Peripheral Configuration Item Values IPMI Boot Parameter Description PCIe SR IOV Support Enabled Disabled pci_sriov Enables Disables PCI Express Single Root I O Virtualization PCIe ARI Enabled Disable...

Page 189: ...pheral Configuration Intel VT for Directed I O VT d Item Values IPMI Boot Parameter Description Intel VT for Directed I O VT d Enabled Disabled vtd Enables Disables Intel Virtualization Technology for Directed I O VT d by reporting the I O device assignment to VMM through DMAR ACPI Tables Interrupt Remapping Enabled Disabled vtd_ir Enables Disables VT_D Interrupt Remapping Support Table 6 5 Advanc...

Page 190: ...Basic Input Output System 190 ATCA 7540 Installation and Use 6806871A01A 6 7 2 4 NVM Express Information 6 7 2 5 USB Configuration Figure 6 13 NVM Express Information Figure 6 14 USB Configuration ...

Page 191: ...ion option 6 7 2 6 Socket Configuration Table 6 7 Advanced USB Configuration Item Values IPMI Boot Parameter Description USB BIOS Support Enabled Disabled UEFI Only usb Enables Disables USB keyboard mouse storage support under UEFI and DOS environment If UEFI Only is set it supports only in UEFI environment Figure 6 15 Socket Configuration ...

Page 192: ... Item Values IPMI Boot Parameter Description Hyper Treading Enabled Disabled cpu_ht Enables Hyper Threading Software Method to Enable Disable logical processor threads Execute Disable Bit Enabled Disabled cpu_ed When Disabled forces the XD feature flag to always return 0 Enable Intel TXT VMX Enabled Disabled cpu_txt Enables Disables the Intel Trusted Execution Technology TXT Hardware Prefetcher En...

Page 193: ...ns that require high utilization of random memory accesses DCU Streamer Prefetcher Enabled Disabled Enables Disables the Data Cache Unit DCU prefetcher DCU IP Prefetcher Enabled Disabled Enables Disables the DCU IP prefetcher LLC Prefetch Enabled Disabled Enables DisablestheLast Level Cache LLC prefetcher Extended APIC Enabled Disabled cpu_x2apic Enables Disables the extended APIC support Table 6 ...

Page 194: ...escriptions for the Per Socket Configuration options Figure 6 17 Per Socket Configuration Table 6 9 Per Socket Configuration Item Values IPMI Boot Parameter Description Core Disable Bitmap 0 to 0xFFFFFFFF Cpu0_dism Cpu 1_dism Core Disable Bitmap Hex Value 0 Enable all Cores Valid Range 0 to 0xFFFFFFFF IOT Cfg Enabled Disabled Configures the bit to enable IOT OCLA ...

Page 195: ...iguration The following table contains the description for the Common RefCode Configuration option Figure 6 18 Common RefCode Configuration Table 6 10 Common RefCode Configuration Item Values IPMI Boot Parameter Description Numa Enabled Disabled mem_numa Enables Disables non uniform memory access NUMA ...

Page 196: ...tions Figure 6 19 Memory Configuration Table 6 11 Memory Configuration Item Values IPMI Boot Parameter Description Memory Frequency Auto 800 2800 mem_speed Maximum Memory Frequency Selections in MHz Halt on mem Training Error Enabled Disabled mem_halt Enables Disables Halt on Memory Training Error Hardware Memory Test Disabled Short Long Mem_test Select Hardware Memory test ...

Page 197: ...y RAS Configuration Table 6 12 Memory RAS Configuration Item Values IPMI Boot Parameter Description Static Virtual Lockstep Mode Enabled Disabled mem_ras Enables Disables virtual lockstep mode Mirror mode Disabled Mirror Mode 1LM Mirror Mode 2LM Disables or selects mirroring mode Memory Rank Sparing mem_sparing Enables Disables Memory Rank Sparing Patrol Scrub mem_ps Enables Disables Patrol Scrub ...

Page 198: ... following table contains descriptions for the CPU P State Control options Figure 6 21 CPU P State Control Table 6 13 CPU P State Control Item Values IPMI Boot Parameter Description SpeedStep Enabled Disabled cpu_ss Enables DisablesEnhancedIntelSpeedStep Technology P States Turbo Mode Enabled Disabled cpu_tm Enables Disables processor Turbo Mode ...

Page 199: ...e Control Item Values IPMI Boot Parameter Description Autonomous Core C State Enabled Disabled cpu_cstates Enables Disables processor idle power saving states C States CPU C6 report Auto Enabled Disabled cpu_c6 Enables Disables CPU C6 ACPI C3 report Enhanced Halt State Enabled Disabled cpu_c1e Enables the Enhanced C1E state of the CPU OS ACPI Cx ACPI C2 ACPI C3 cpu_cxacpi Report CPU C3 C6 state to...

Page 200: ... Control option Figure 6 23 Package C State Control Table 6 15 Package C State Control Item Values IPMI Boot Parameter Description Package C State C0 C1 state C2 state C6 non Retention state C6 Retention state No Limit Auto cpu_cslimit Specifies the lowest C state for the package Higher C states will save more power lower C states will have lower wake up latencies ...

Page 201: ...00 VT_100 VT_UTF8 PC_ANSI con_tt Sets Console Redirection terminal type Baud Rate 115200 57600 38400 19200 9600 4800 2400 1200 con_br Sets Console Redirection baud rate Data Bits 7 Bits 8 Bits con_db Sets Console Redirection data bits Parity None Even Odd con_par Sets Console Redirection parity bits Stop Bits 1 Bit 2 Bits con_sb Sets Console Redirection stop bits Flow Control None XON XOFF con_fc ...

Page 202: ...ort Enabled Disabled apei Disables Enables ACPI Platform Error Interface APEI and Windows Hardware Error Architecture WHEA AEPI extends hardware error reporting mechanisms and brings them together as components of a coherent hardware error infrastructure APEI Error Injection Disabled MEMORY_CE MEMORY_UE_NON_FATAL MEMORY_UE_FATAL PCIE_CE PCIE_UE_FATAL PCIE_UE_NON_FATAL Inject an error to test APEI ...

Page 203: ...anced H2O Event Log Config Manager Event and Message Pages BIOS Event Log Viewer Item Values IPMI Boot Parameter Description Log Event To ALL BIOS BMC SEL MEMORY Settings Events to log Selected Storage Figure 6 26 IPMI OEM Configuration Table 6 19 Advanced IPMI Configuration Item Values IPMI Boot Parameter Description IPMI KCS Interrupt Enabled Disabled ipmi_irq Enables Disables usage of Host Inte...

Page 204: ...figure the Timeout of the OS Boot Watchdog Timer OS WD Timeout Action No Action Hard Reset Power Down Power Cycle osboot_wd_acti on Configure how the system should respond if the OS Boot Watchdog Timer expires IPMI Fail Safe Enabled Disabled No Change failsafe Enables Disables Fail Safe Policy Enabled IPMC will switch the BIOS boot bank if the FRB2 watchdog expires No Change Fail Safe Policy will ...

Page 205: ...y configuration options Figure 6 27 Security Configuration Table 6 20 Security Item Values IPMI Boot Parameter Description TPM Operation No Operation Disable and Deactivate Enable and Activate tpm_operation Enables DisablesTPMFunction Thisoption will automatically return to No Operation Set Supervisor Password Install or Change the password The length of password must be greater than one character...

Page 206: ...Boot Parameter Description Boot Type Dual Boot Type Legacy Boot Type UEFI boot Type boot_type Select boot type to Dual type Legacy type or UEFI type Dual boot type supports boot from Legacy and UEFI Boot Priority EFI First Legacy First boot_priority Determine whether EFI devices or Legacy devices are booted first PXE Boot capability Disabled UEFI IPv4 UEFI IPv6 UEFI IPv4 IPv6 Legacy boot_netprot D...

Page 207: ...s execution of the Option ROM for all Fabric Network Ethernet controller Select Enabled whenFabric Network Boot is required RTM Network Boot Enabled Disabled boot_rtmnet Controls execution of the Option ROM for RTM Network Ethernet controller Select Enabled when RTM Network Boot is required RTM SAS Boot Enabled Disabled boot_artmsas Controls execution of the Option ROM for RTM SAS controller Selec...

Page 208: ...nfigure the order of the EFI Boot devices Use the Up and Down keys to select a device Use the F5 key to move the devices up or down With the space key a boot device can be enabled or disabled If the boot entry shows this boot entry is disabled If it shows X then the boot devices is enabled Figure 6 29 EFI Boot Order ...

Page 209: ...the order of the Legacy Boot devices Use the Up and Down keys to select a device Use the F5 and F6 keys to move the devices up or down With the space key a boot device can be enabled or disabled If the boot entry shows this boot entry is disabled If it shows X then the boot devices is enabled Figure 6 30 Legacy Boot Order ...

Page 210: ...menu options available Figure 6 31 Exit Menu Table 6 22 Exit Menu Item Values IPMI Boot Parameter Description Exit Saving Changes Saves the changes made and then exits the system Save Change Without Exit Saves the changes without exiting the system Exit Discarding Changes Exits the system without saving the changes Load Defaults Loads default Settings Discard Changes Discards the changes ...

Page 211: ...store Secure Boot to Factory Settings setup item This activates UEFI Secure Boot 5 Press F10 key to save the changes 6 9 Restoring BIOS Default Settings The blade provides an on board configuration switch that allows to load BIOS settings from the DEFAULT area of the IPMI Boot Parameters To restore the BIOS default settings 1 Remove the blade from the system 2 Set the on board switch SW3 4 to ON S...

Page 212: ...ructure 1 UUID Shows SEL and Sensor Values in BIOS setup BIOS creates the DMI structure type 38 to provide IPMI host interface information to the OS BIOS reads and creates the IPMI boot parameters which are stored in the IPMC 6 11 Watchdog Support BIOS uses the IPMI payload watchdog for two phases BIOS phase Operation System boot phase The IPMC starts automatically the IPMI payload watchdog after ...

Page 213: ...Error Logging Errors are logged to the IPMI controller 6 12 2 IPMI Error Logging BIOS generates status events like Firmware Progress events and error events Table 6 23 Logged Error Events Error IPMI Correctable Correctable ECC Memory Error Sensor Memory Offset 00h Correctable Memory Error Limit Reached Correctable ECC logging limit reached Sensor Memory Offset 05h Uncorrectable Uncorrectable ECC M...

Page 214: ...n Divide Error 31h Exception Invalid Opcode 32h Exception Stack Fault 33h Exception GP Fault 34h Exception Math Error 35h Exception Alignment Check 36h Exception Machine Check 50h IPMI Boot Parameter Default Area Read Error 51h IPMI Boot Parameter Default Area Locked 52h IPMI Boot Parameter Default Area Checksum Error 53h IPMI Boot Parameter User Area Read Error 54h IPMI Boot Parameter User Area L...

Page 215: ... initialization 09h Video initialization 0Ah Cache initialization 0Ch Console input initialization 13h Starting Operating System FDh OEM Error Extension Supported Event Data3 FDh OEM Error Extension 90h Reboot after a FRB2 Watchdog Timeout 91h Reboot after a BIOS POST Watchdog Timeout 92h Reboot after a OS Load Watchdog Timeout 93h Reboot after a SMS OS Watchdog Timeout 94h Reboot after a OEM Watc...

Page 216: ...t 01h Uncorrectable ECC Offset 04h Memory Device Disabled Offset 05h Correctable ECC error logging limit reached Offset 06h Presence detected Event Data2 0xFF Event Data3 Bit Description 0 3 Sequential DIMM number 1 to 8 4 7 CPU Socket 1 to 2 See Figure 2 2 ATCA 7540 Blade Layout on page 51 for DIMM naming convention Critical Interrupt 13h Offset 04h PCI PERR Offset 05h PCI SERR Event Data2 Bus nu...

Page 217: ...ained by reading the POST code on board IPMI sensor The reading of the POST code sensor is only valid when the blade is in the BIOS phase The reading can be used to locate the cause of a blade hang during BIOS phase When the blade has booted a OS the reading of the POST code sensor returns no valid status code For debugging purpose the POST Codes can be printed to the serial console by setting DIP...

Page 218: ...l 79h SMBUS Early Initial 7Ah Clock Generator Initial 7Bh Internal Graphic device early initial PEI_IGDOpRegion 7Ch HECI Initial 7Dh Watchdog timer initial 7Eh Memory Initial for Normal boot 7Fh Memory Initial for Crisis Recovery 80h Simple Memory test 81h TXT function early initial 82h Start to use Memory 83h Set cache for physical memory 84h Recovery device initial 85h Found Recovery image 86h R...

Page 219: ...ge Middle initial 46h Super I O DXE initial 47h Setup Legacy Region service DXE_LegacyRegion 48h South Bridge Middle Initial 49h Identify Flash device 4Ah Fault Tolerant Write verification 4Bh Variable Service Initial 4Ch Fail to initial Variable Service 4Dh MTC Initial 4Eh CPU Middle Initial 4Fh Multi processor Middle Initial 50h SMBUS Driver Initial 51h 8259 Initial 52h RTC Initial 53h SATA Cont...

Page 220: ...age collection and reclaim operation 62h Do not support flash part which is defined in SpiDevice c 10h Enter BDS entry 11h Install Hotkey service 12h ASF Initial 13h PCI enumeration 14h PCI resource assign complete 15h PCI enumeration complete 16h Keyboard Controller Keyboard and Moust initial 17h Video device initial 18h Error report device initial 19h USB host controller initial 1Ah USB BUS driv...

Page 221: ... 29h Enter Setup Menu 2Ah Enter Boot manager 2Bh Try to boot system to OS 2Ch Shadow Misc Option ROM 2Dh Save S3 resume required data in RAM 2Eh Last Chipset initial before boot to OS 2Fh Start to boot Legacy OS 30h Start to boot UEFI OS 31h Prepare to Boot to Legacy OS 32h Send END of POST Message to ME via HECI 33h Last Chipset initial before boot to Legacy OS 34h Ready to Boot Legacy OS 35h Fas...

Page 222: ...function A9h ACPI disable function complete C0h Memory initial for S3 resume C1h Get S3 resume required data from memory C2h Start to use memory during S3 resume C3h Set cache for physical memory during S3 resume C4h Start to restore system configuration C5h Restore system configuration stage 1 C6h Restore system configuration stage 2 C7h Relocate SMM BASE during S3 resume C8h Multi processor init...

Page 223: ...cess the config space A5h UPI Initialization System configurations that require some kind of reset A6h UPI Initialization Sync up with PBSPs A7h UPI Initialization Topology discovery and route calculation A8h UPI Initialization Program final route A9h UPI Initialization Program final IO SAD setting AAh UPI Initialization Protocol layer and other Uncore settings ABh UPI Initialization Transition li...

Page 224: ...ion JEDEC Init B7h Memory Initialization Channel Training B8h Memory Initialization Throttling Init B9h Memory Initialization BIST BAh Memory Initialization Init BBh Memory Initialization DDR Memory Mapping BCh Memory Initialization RAS Configuration BDh Memory Initialization Get Margins BFh Memory Initialization MRC Done Table 6 25 BIOS POST Codes continued POST Code Description ...

Page 225: ...es The sideband interface of the Intel NIC is used to transmit receive its terminal characters via a base interface You can configure the SOL parameters using ipmitool The ATCA 7540 supports two SOL channels which are available at their base interfaces However only one SOL session is allowed at a time Figure 7 1 SOL Overview Faceplate FPGA IPMC CPU Intel NIC Serial LPC Serial Serial NC SI PCIe Eth...

Page 226: ...able on this site 7 3 Configuring SOL Parameters You can configure the following SOL parameters You can use ipmitool to modify the parameters 7 3 1 Using ipmitool The following examples show how to query the LAN parameters that are currently in use for a potential SOL session for base 1 or base 2 root ATCA 7540 ipmitool lan print 1 Set in Progress Set Complete Auth Type Support Auth Type Enable Ca...

Page 227: ...Support Auth Type Enable Callback User Operator Admin OEM IP Address Source Unspecified IP Address 172 17 1 220 Subnet Mask 255 255 0 0 MAC Address ec 9e cd 10 a0 65 Default Gateway IP 172 17 0 1 Default Gateway MAC 00 00 00 00 00 00 RMCP Cipher Suites 1 2 3 3 Cipher Suite Priv Max Not Available You canchangetheIPMCLANparameters using the ipmitool lan set commands For example to change the IP addr...

Page 228: ... address on the 172 16 0 0 16 subnet to this base1 interface before attempting an SOL activation If you have less leeway to changing the base1 IP address on the initiator blade you could leave this base1 IP address on the initiator blade as is and instead change the IP address assigned to the IPMC LAN 1 interface on the ATCA 7540 blade to be on the same subnet as the base1 interface on the initiat...

Page 229: ...able 8 1 Supported Global IPMI Commands Command NetFn Request Response CMD Comments Get Device ID 0x06 0x07 0x01 Cold Reset 0x06 0x07 0x02 Warm Reset 0x06 0x07 0x03 Get Self Test Results 0x06 0x07 0x04 Get Device GUID 0x06 0x07 0x08 Master Write Read 0x06 0x07 0x52 Only for accessing private I C buses Table 8 2 Supported System Interface Commands Command NetFn Request Response CMD Set BMC Global E...

Page 230: ...ess 0x06 0x07 0x44 Set User Name 0x06 0x07 0x45 Get User Name 0x06 0x07 0x46 Set User Password 0x06 0x07 0x47 Set User Payload Access 0x06 0x07 0x4C Get User Payload Access 0x06 0x07 0x4D Set Channel Security Keys 0x06 0x07 0x5C Table 8 2 Supported System Interface Commands continued Command NetFn Request Response CMD Table 8 3 Supported Watchdog Commands Command NetFn Request Response CMD Reset W...

Page 231: ...A 0x0B 0x49 Table 8 4 Supported SEL Device Commands continued Command NetFn Request Response CMD Table 8 5 Supported FRU Inventory Commands Command NetFn Request Response CMD Get FRU Inventory Area Info 0x0A 0x0B 0x10 Read FRU Data 0x0A 0x0B 0x11 Write FRU Data 0x0A 0x0B 0x12 Table 8 6 Supported Sensor Device Commands Command NetFn Request Response CMD Comments Get Device SDR Info 0x04 0x05 0x20 G...

Page 232: ...et Sensor Threshold 0x04 0x05 0x27 Set Sensor Event Enable 0x04 0x05 0x28 Get Sensor Event Enable 0x04 0x05 0x29 Get Sensor Event Status 0x04 0x05 0x2B Get Sensor Reading 0x04 0x05 0x2D Get Sensor Type 0x04 0x05 0x2F Set Event Receiver 0x04 0x05 0x00 Get Event Receiver 0x04 0x05 0x01 Platform Event 0x04 0x05 0x02 Table 8 6 Supported Sensor Device Commands continued Command NetFn Request Response C...

Page 233: ...different purposes When using the Get Set System Boot Options commands except for parameter 100 use the response request data fields with the Set Selector and the Block Selector set to 0x00 When using the Get Set System Boot Option for the parameter 100 the Set Selector and the Block Selector have a specific meaning For more details see System Boot Options Parameter 100 on page 235 for details The...

Page 234: ...stream from default boot flash 1 Load configuration stream from backup boot flash Note The new FPGA configuration stream is loaded into the FPGA at the next power up of the payload Bit 0 Default backup boot flash selection 0 Boot from default boot flash 1 Boot from backup boot flash Note The newly selected boot flash is connected to the payload immediately which means that the writing to the flash...

Page 235: ...pose is to store factory programmed default boot options which can be used to restore the standard settings If you want the BIOS to read out and use the boot parameters stored in the default area and thus use the factory settings you need to configure the blade accordingly This is typically done by an on board switch for example Clear CMOS RAM The settings stored in the default area are dependent ...

Page 236: ... The number of bytes must be calculated and written into these two bytes by the software which writes into the storage area The values 0x0000 and 0xFFFF indicate that no data has been written to the storage area When reading from the storage area andyoufindanyofthesetwovalues yoursoftwareshouldassumethatnouser specific boot options have previously been written to the storage area 2 n Boot paramete...

Page 237: ...ed again after the final access Bits 6 0 must contain the value 100 indicating this OEM system boot option 2 Set Selector Must be set to 0 user area You can only write to the user area therefore no other values are supported 3 Block Selector Zerobasedindexofthe16 byteblockwhichyouwanttowriteto Index 0 refers to the first block of 16 bytes which includes the first two bytes that indicate the boot p...

Page 238: ...orage not supported by the IPMC 0xC9 Block selector is outside of the allowed range 2 Reserved Set to 1 3 Bit 7 If set to 1 the addressed storage area is locked Bits 6 0 value 100 indicating thisOEM boot option command 4 19 The content of the read 16 byte block In order to detect the maximum size of writable storage area your software can perform a series of read accesses while incrementing the bl...

Page 239: ... RTM PCIe parameter can be set manually on off rtm_cpu0_bif Selects CPU0 PCIe Bifurcation for Zone 3 connector RTM X4x4x4x4 x4x4x8 x8x4x4 x8x8 rtm_cpu0_3a Selects CPU0 PCIe Port 3A Speed for Zone 3 connector RTM auto gen1 gen2 gen3 rtm_cpu0_3b Selects CPU0 PCIe Port 3B Speed for Zone 3 connector RTM auto gen1 gen2 gen3 rtm_cpu0_3c Selects CPU0 PCIe Port 3C Speed for Zone 3 connector RTM auto gen1 ...

Page 240: ..._3d Selects CPU1 PCIe Port 3D Speed for Zone 3 connector RTM auto gen1 gen2 gen3 pci_sriov PCI Express Single Root I O Virtualization on off pci_ari Alternative Routing ID nterpretation ARI on off pci_64bit 64 bit BAR support for PCI devices on off clock_ssc Spread Spectrum Clock on off vtd Intel Virtualization Technology for Directed I O VT d on off vtd_ir VT d Interrupt Remapping Support on off ...

Page 241: ...Range 0to3FFE 3FFF Disabling all cores Invalid Hex Value 0 to FFFF cpu1_dism Core Disable Bitmap Hex Value 0 Enable all cores ValidRange 0to3FFE 3FFF Disabling all cores Invalid Hex Value 0 to FFFF cpu_ht CPU Hyper Threading on off cpu_ed CPU Execute Disable on off cpu_txt Intel Trusted Execution Technology TXT on off cpu_vt CPU Virtualization VT x on off cpu_hp CPU Hardware Prefetcher on off cpu_...

Page 242: ... cpu_cslimit Package C State limit c0c1 c2 c6nr c6r no cpu_c3 CPU C3 report on off cpu_c6 CPU C6 report on off cpu_c1e CPU Enhanced Halt State C1E on off cpu_cxacpi Report ACPI Cx State c2 c3 mem_speed Memory Frequency MHz auto 1333 1600 1867 2133 mem_halt Halt on Training Error on off mem_numa Disable Non Uniform Memory Access NUMA on off Table 8 14 System Boot Options Parameter 100 Supported Par...

Page 243: ...Serial console terminal type vt100 vt100 utf8 ansi con_br Serial console baud rate 9600 19200 38400 57600 115200 con_db Serial console data bits 7 8 con_par Serial console parity bits o e o con_sb Serial console stop bits 1 2 con_fc Serial console flow control off hard soft con_ap Serial console redirection after POST on off Table 8 14 System Boot Options Parameter 100 Supported Parameters continu...

Page 244: ... 15 20 osboot_wd_action 0S Watchdog Timeout Action noaction reset poweroff powercycle failsafe IPMI Fail Safe on off nochange tpm_operation TPM Function This option will automatically return to No Operation no_operation disable_deactivate enable_activate boot_type Boot Type dual legacy uefi boot_priority Determine whether EFI devices or Legacy devices are booted first uefi legacy Table 8 14 System...

Page 245: ...oot_usb USB device boot on off info_tmout The number of seconds that the firmware will wait for F2 key on off boot_order Set the Boot Order See Table 8 15 device1 deviceN separated by comma Table 8 14 System Boot Options Parameter 100 Supported Parameters continued Parameter Description Values Table 8 15 Boot Order Devices Boot Device Description sata0 On board SATA device P1 sata1 On board SATA d...

Page 246: ... fabricnet22 Fabric Network 2_2 rtmnet1 RTM Network 1 rtmnet2 RTM Network 2 rtmnet3 RTM Network 3 rtmnet4 RTM Network 4 rtmnet5 RTM Network 5 rtmnet6 RTM Network 6 rtmnet7 RTM Network 7 rtmnet8 RTM Network 8 rtmnet9 RTM Network 9 rtmnet10 RTM Network 10 usbcdrom USB CDROM DVDROM usbcdrom1 USB CDROM DVDROM connected to USB1 usbcdrom2 USB CDROM DVDROM connected to USB2 usbcdrom3 USB CDROM DVDROM con...

Page 247: ...work 1 IPv4 efirtmnet2 EFI RTM Network 2 IPv4 efirtmnet3 EFI RTM Network 3 IPv4 efirtmnet4 EFI RTM Network 4 IPv4 efirtmnet5 EFI RTM Network 5 IPv4 efirtmnet6 EFI RTM Network 6 IPv4 efirtmnet7 EFI RTM Network 7 IPv4 efirtmnet8 EFI RTM Network 8 IPv4 efirtmnet9 EFI RTM Network 9 IPv4 efirtmnet10 EFI RTM Network 10 IPv4 eiffrontnet1v6 EFI Front Panel Network 1 IPv6 efifrontnet2v6 EFI Front Panel Net...

Page 248: ... Network 6 IPv6 efirtmnet7v6 EFI RTM Network 7 IPv6 efirtmnet8v6 EFI RTM Network 8 IPv6 efirtmnet9v6 EFI RTM Network 9 IPv6 efirtmnet10v6 EFI RTM Network 10 IPv6 efiusb EFI Boot from USB device efiusb1 EFI Boot from USB device connected to USB1 efiusb2 EFI Boot from USB device connected to USB2 eifusb3 EFI Boot from USB device connected to USB RTM windows Windows Boot Manager redhat RedHat Linux s...

Page 249: ...ters 0x0C 0x0D 0x01 Get LAN Configuration Parameters 0x0C 0x0D 0x02 Set SOL Configuration Parameters 0x0C 0x0D 0x21 Get SOL Configuration Parameters 0x0C 0x0D 0x22 Table 8 17 Supported PICMG 3 0 Commands Command NetFn Request Response CMD Comments Get PICMG Properties 0x2C 0x2D 0x00 Get Address Info 0x2C 0x2D 0x01 FRU Control 0x2C 0x2D 0x04 The blade supports the cold reset and graceful reboot opt...

Page 250: ...C Port State 0x2C 0x2D 0x19 Get AMC Port State 0x2C 0x2D 0x1A Get FRU Control Capabilities 0x2C 0x2D 0x1E Get target upgrade capabilities 0x2C 0x2D 0x2E Get component properties 0x2C 0x2D 0x2F Abort firmware upgrade 0x2C 0x2D 0x30 Initiate upgrade action 0x2C 0x2D 0x31 Upload firmware block 0x2C 0x2D 0x32 Finish firmware upload 0x2C 0x2D 0x33 Get upgrade status 0x2C 0x2D 0x34 Activate firmware 0x2...

Page 251: ...according to the PICMG HPM 1 Revision 1 0 specification The boot block can be updated with PICMG HPM 1 specific commands Before sending any of these commands the shelf management software must check whether the receiving IPMI controller supports Artesyn Embedded Technologies specific IPMI commands by using the IPMI command Get Device ID Sending Artesyn specific commands to IPMI controllers which d...

Page 252: ...s to be used 3 MSB of Artesyn Embedded Technologies IANA Enterprise number A value of 0x00 has to be used 4 Serial connector type 0 Faceplate connector 1 Backplane connector All other values are reserved Note Only the faceplate connector is supported No connector on the RTM available 5 Serial connector instance number A sequential number that starts from 0 6 Serial output selector 0 BIOS 2 IPMC de...

Page 253: ...equest Data of Get Serial Output Command Byte Data Field 1 LSB of Artesyn Embedded Technologies IANA Enterprise number A value of 0xCD has to be used 2 Second byte of Artesyn Embedded Technologies IANA Enterprise number A value of 0x65 has to be used 3 MSB of Artesyn Embedded Technologies IANA Enterprise number A value of 0x00 has to be used 4 Serial connector type 0 Faceplate connector 1 Backplan...

Page 254: ...ata of Get Serial Output Command Byte Data Field 1 Completion code 2 LSB of Artesyn Embedded Technologies IANA Enterprise number 3 Second byte of Artesyn Embedded Technologies IANA Enterprise number 4 MSB of Artesyn Embedded Technologies IANA Enterprise number 5 Serial output selector Table 8 23 Feature Configuration Command Command NetFn Request Response CMD Defined In Set Feature Configuration 0...

Page 255: ...ails see Table 8 25 5 Feature Configuration Bit 7 0 Feature Selector E0h E1h 00h disabled 01h enabled 02h 0ffh reserved Bit 7 0 Feature Selector 03h 00h FFh Debounce timer timeout value in 100ms 6 Persistency Duration 00h volatile Actual duration depends on implementation 01h FFh reserved Response Data 1 Completion Code Generic plus the following command specific completion codes 80h feature selec...

Page 256: ...ector Description 3 03h Handle Debounce 224 E0h FAILSAFE Function Enable Disable For details see Fail Safe Logic on page 314 225 E1h FAIL PROTECT Function Enable Disable For details see Fail Protect Logic on page 317 Table 8 26 Get Feature Configuration Command Type Byte Data Field Request Data 1 LSB of Artesyn IANA Enterprise Number A value of CDh shall be used 2 2ndbyteofArtesynIANAEnterpriseNum...

Page 257: ...er A value of CDh shall be used 3 2ndbyteofArtesynIANAEnterpriseNumber Avalueof65hshallbe used 4 MSB of Artesyn IANA Enterprise Number A value of 00h shall be used 5 Feature Configuration Bit 7 0 Feature Selector E0h E1h 00h disabled 01h enabled 02h 0ffh reserved Bit 7 0 Feature Selector 03h 00h FFh Debounce timer timeout value in 100 ms 6 Persistency Duration Table 8 26 Get Feature Configuration ...

Page 258: ...2 on page 264 0x2E 0x2F 0x03 Set Debug Level Table 8 33 on page 265 0x2E 0x2F 0x04 Get Hardware Address Table 8 34 on page 266 0x2E 0x2F 0x05 Set Hardware Address Table 8 35 on page 266 0x2E 0x2F 0x06 Get Handle Switch Table 8 36 on page 267 0x2E 0x2F 0x07 Set Handle Switch Table 8 37 on page 267 0x2E 0x2F 0x08 Get Payload Communication Time Out Table 8 38 on page 268 0x2E 0x2F 0x09 Set Payload Co...

Page 259: ... but keeps on listening to the serial debug and payload interfaces and serving requests coming from them as well as managing the modules AMC point to point P2P and clock E keying Standalone mode is intended for debugging purposes and or operation in a non ATCA environment In standalone mode thecarrier IPMC automaticallyactivatesand deactivatestheon carrierpayload and modules whenever it does not v...

Page 260: ...nostic interrupt request has arrived Bit 5 Shutdown Alert If set to 1 indicates that the payload is going to be shutdown Bit 4 Reset Alert If set to 1 indicates that the payload is going to be reset Bit 3 Sensor Alert If set to 1 indicates that at least one of the IPMC sensors detects a threshold crossing Bits 2 1 Mode The current IPMC modes are defined as 0 Normal 1 Standalone for a description r...

Page 261: ...rce 3 Metallic Bus 1 Free 7 Bits 4 7 Clock Bus 2 Events These bits indicate pending Clock Bus 2 requests arrived from the shelf manager 0 Clock Bus 2 Query 1 Clock Bus 2 Release 2 Clock Bus 2 Force 3 Clock Bus 2 Free Bits 0 3 Clock Bus 1 Events These bits indicate pending Clock Bus 1 requests arrived from the shelf manager 0 Clock Bus 1 Query 1 Clock Bus 1 Release 2 Clock Bus 1 Force 3 Clock Bus 1...

Page 262: ...prise ID 0x00400A 16394 Pigeon Point Systems LSB Byte first byte 1 0A byte 2 40 byte 3 00 4 Interface ID 0 Serial Debug Interface Response Data 1 Completion Code 2 4 PPS IANA Private Enterprise ID 0x00400A 16394 Pigeon Point Systems LSB Byte first byte 2 0A byte 3 40 byte 4 00 5 Bit 7 Echo On If this bit is set the IPMC enables echo for the given serial interface Bits 6 4 Reserved Bits 3 0 Baud Ra...

Page 263: ...prise ID 0x00400A 16394 Pigeon Point Systems LSB Byte first byte 1 0A byte 2 40 byte 3 00 4 Interface ID 0 Serial Debug Interface 5 Bit 7 Echo On If this bit is set the IPMC enables echo for the given serial interface Bits 6 4 Reserved Bits 3 0 Baud Rate ID The baud rate ID defines the interface baud rate as follows 0 9600 bps 1 19200 bps 2 38400 bps 3 57600 bps unsupported 4 115200 bps unsupporte...

Page 264: ...nable If set to 1 theIPMC provides atraceof IPMB Lmessages that are arriving to going from the IPMC via IPMB L Bit 6 n a Bit 5 KCS Dump Enable If set to 1 the IPMC provides a trace of KCS messages that are arriving to going from the IPMC via KCS Bit 4 IPMB Dump Enable If set to 1 the IPMC provides a trace of IPMB messages that are arriving to going from the IPMC via IPMB O Bit 3 n a Bit 2 Alert Lo...

Page 265: ...et to 1 the IPMC provides a trace of KCS messages that are arriving to going from the IPMC via KCS Bit 4 IPMB Dump Enable If set to 1 the IPMC provides a trace of IPMB messages that are arriving to going from the IPMC via IPMB O Bit 3 n a Bit 2 Alert Logging Enable If set to 1 the IPMC outputs important alert messages onto the serial debug interface Bit 1 Low level Error Logging Enable If set to 1...

Page 266: ...te first byte 1 0A byte 2 40 byte 3 00 Response Data 1 Completion Code 2 4 PPS IANA Private Enterprise ID 0x00400A 16394 Pigeon Point Systems LSB Byte first byte 2 0A byte 3 40 byte 4 00 5 Hardware Address Table 8 35 Set Hardware Address Command Description Type Byte Data Field Request Data 1 3 PPS IANA Private Enterprise ID 0x00400A 16394 Pigeon Point Systems LSB Byte first byte 1 0A byte 2 40 by...

Page 267: ...on Point Systems LSB Byte first byte 1 0A byte 2 40 byte 3 00 Response Data 1 Completion Code 2 4 PPS IANA Private Enterprise ID 0x00400A 16394 Pigeon Point Systems LSB Byte first byte 2 0A byte 3 40 byte 4 00 5 Handle Switch Status 0x00 The handle switch is open 0x01 The handle switch is closed 0x02 The handle switch state is read from hardware Table 8 37 Set Handle Switch Command Description Typ...

Page 268: ...de 2 4 PPS IANA Private Enterprise ID 0x00400A 16394 Pigeon Point Systems LSB Byte first byte 2 0A byte 3 40 byte 4 00 5 Payload Time out Payload communication time out measured in hundreds of milliseconds Thus the payload communication time out may vary from 0 1 to 25 5 seconds Table 8 39 Set Payload Communication Time Out Command Description Type Byte Data Field Request Data 1 3 PPS IANA Private...

Page 269: ...ta 1 3 PPS IANA Private Enterprise ID 0x00400A 16394 Pigeon Point Systems LSB Byte first byte 1 0A byte 2 40 byte 3 00 Response Data 1 Completion Code 2 4 PPS IANA Private Enterprise ID 0x00400A 16394 Pigeon Point Systems LSB Byte first byte 2 0A byte 3 40 byte 4 00 Table 8 41 Disable Payload Control Command Description Type Byte Data Field Request Data 1 3 PPS IANA Private Enterprise ID 0x00400A ...

Page 270: ...x00 Cold IPMC reset to the Current mode 0x01 Cold IPMC reset to the Normal mode 0x02 Cold IPMC reset to the Standalone mode for a description refer to Table 8 28 0x03 Cold IPMC reset to the Manual Standalone mode for a description refer to Table 8 28 0x04 Reset the IPMC and enter Upgrade mode Response Data 1 Completion Code 2 4 PPS IANA Private Enterprise ID 0x00400A 16394 Pigeon Point Systems LSB...

Page 271: ...e completion of the payload shutdown sequence 8 4 17 Get Payload Shutdown Time Out Command When shelf manager commands the IPMC to shut down the payload sends the Activate FRU Deactivate command the IPMC notifies the payload by forwarding the command Activate FRU Deactivate to the KCS interface Provided the OpenIPMI driver has registered this command for notification the payload gets notified Upon...

Page 272: ...Type Byte Data Field Request Data 1 3 PPS IANA Private Enterprise ID 0x00400A 16394 Pigeon Point Systems LSB Byte first byte 1 0A byte 2 40 byte 3 00 Response Data 1 Completion Code 2 4 PPS IANA Private Enterprise ID 0x00400A 16394 Pigeon Point Systems LSB Byte first byte 2 0A byte 3 40 byte 4 00 5 6 Time Out measured in hundreds of milliseconds LSB first Table 8 46 Set Payload Shutdown Time Out C...

Page 273: ...ID Response Data 1 Completion Code 2 4 PPS IANA Private Enterprise ID 0x00400A 16394 Pigeon Point Systems LSB Byte first byte 2 0A byte 3 40 byte 4 00 5 Module Status Bit 0 0 Module site is enabled 1 Module site is disabled Bit 1 0 Module is not present 1 Module is present Bit 2 0 Management power is disabled 1 Management power is enabled Bit 3 0 Management power is bad 1 Management power is good ...

Page 274: ...equest Data 1 3 PPS IANA Private Enterprise ID 0x00400A 16394 Pigeon Point Systems LSB Byte first byte 1 0A byte 2 40 byte 3 00 4 Module Site ID Response Data 1 Completion Code 2 4 PPS IANA Private Enterprise ID 0x00400A 16394 Pigeon Point Systems LSB Byte first byte 1 0A byte 2 40 byte 3 00 Table 8 49 Disable Module Site Command Description Type Byte Data Field Request Data 1 3 PPS IANA Private E...

Page 275: ... the carrier SDR repository Table 8 50 Reset Carrier SDR Repository Command Description Type Byte Data Field Request Data 1 3 PPS IANA Private Enterprise ID 0x00400A 16394 Pigeon Point Systems LSB Byte first byte 1 0A byte 2 40 byte 3 00 Response Data 1 Completion Code 2 4 PPS IANA Private Enterprise ID 0x00400A 16394 Pigeon Point Systems LSB Byte first byte 2 0A byte 3 40 byte 4 00 ...

Page 276: ...Supported IPMI Commands 276 ATCA 7540 Installation and Use 6806871A01A ...

Page 277: ... Interface IPMI commands and provides hardware interfaces for other system management features such as Hot Swap control LED control power control as well as temperature and voltage monitoring The IPMC also supports a Keyboard Controller Style KCS based host interface for direct payload to IPMI communication The ATCA 7540 provides a rich feature set Carrier SDR Repository FRU inventory Sensor Manag...

Page 278: ...ill be bridged by the IPMC The Intel CPU communicates with the IPMC using the KCS interface of the IPMC The FRU inventory System Event Log SEL events and the SDR information are stored in external I C EEPROMs This enables post mortem analysis when the system processor becomes disabled Registers within the Glue Logic FPGA can be accessed by the IPMC via I C bus This enhances the capabilities of the...

Page 279: ...2C IPMB A IPMB B IPMB L I2C B u f f e r B u f f e r LPC Microsemi A2F200M3F_CS2 88 IPMC PCH ME 0x96 0x98 Intel CPU Intel NIC SOL ATMEGA 128 MMC at RTM NCSI Lattice GLUE FPGA 0xFD 0xFE FRU EEPROM 0xA2 SEL EEPROM 0xA0 PIM 0x50 PCA9555 0x48 WDT WDT Cortex M3 ADT ADT LM75 outlet LM75 inlet LM75 TEMP Front Front RTM I2C ...

Page 280: ...is responsible for providing a means for measuring time and detecting timeout conditions The device drivers are responsible for implementing high level interfaces to the hardware Network Stack The Network Stack is provided to implement RMCP protocols for IPMI over LAN and Serial over LAN Application Layer The Application Layer is implemented as a multi threaded application The main thread reads in...

Page 281: ...C x KCS IPMB 0 IPMB L Interface Communication x Standalone Mode Hardware Abstraction Layer Application Layer x Firmware Validation Upgrade x POST x Boot x IRQ Handlers x Low Level Initialization x I O Device Drivers x Ethernet Drivers x IP Stack Hardware Boot Loader Network Stack IPMC Active IMPI Firmware x FRU Hot Swap Management IPMC x Sensor Management x FRU Inventory x Carrier SDR Repository I...

Page 282: ...rnal eNVM depending on the successful boot flags NOTE The boot loader is also used as an HPM 1 component however there is no backup image Table 9 1 HPM 1 Components ID Payload coldreset required Deferred activation support Comparison support Preparation support Rollback backup support Component name IPMI boot loader 1 no no yes yes no IPMC B L IPMI firmware 0 yes yes yes yes supported without back...

Page 283: ...Application Programming IAP Component The BMR A2F AMCc IPMI building block from Pigeon Point is implemented within an FPGA logic block from MicrosemiInc Its fabric canbeupgraded via an HPM 1 firmwareupgrade This process is referred to as an In Application Programming IAP upgrade NOTE There is no possibility of crisis recovery Artesyn does not recommend an unnecessary component upgrade 9 3 1 3 FPGA...

Page 284: ... details see System Boot Options Commands on page 233 Automatic rollback is implemented via fail safe architecture For details see Fail Safe Logic on page 314 The HPM 1 command Activate Firmware does not reboot the payload firmware unconditionally The blade can be rebooted gracefully to activate the firmware Crisis recovery is fully supported Corrupted SPI flash components can be reprogrammed via ...

Page 285: ...A Bank 0 Active Version 0 00 00000014 Bank 1 Rollback Version 0 00 00000014 Bank marked for next use 0 05 Device PYLD F W Bank 0 Active Version 1 00 00000004 Bank 1 Rollback Version 1 00 00000001 Bank marked for next use 0 REPORT END 9 3 3 Firmware Upgrade Tool The primary update mechanism for the ATCA 7540 blade is the FCU tool which is delivered with the BBS package for the blade The ATCA 7540 b...

Page 286: ...yload is through the KCS interface The images and the ipmitool need to be on the payload to upgrade Example prompt ipmitool hpm upgrade file 9 3 3 2 2 IPMB 0 This interface represents the backplane IPMI bus and allows remote firmware upgrade The count of the simultaneous upgrades is limited because of the bus speed Examples From shelf manager prompt ipmitool t 0x92 hpm upgrade file With RMCP promp...

Page 287: ...tool also supports large IPMI messages over LAN The following example is provided to enable users to upgrade their firmware quickly from the payload host one BIOS SPI flash can be upgraded in 5 minutes 1 Evaluate IP address of IPMC root ATCA 7540 ipmitool lan print 1 Set in Progress Set Complete Auth Type Support Auth Type Enable Callback User Operator Admin OEM IP Address Source Static Address IP...

Page 288: ...ent 1 0 9 Validating firmware image integrity OK Performing preparation stage Services may be affected during upgrade Do you wish to continue y n y OK Performing upgrade stage ID Name Versions Active Backup File 6 PYLD F W 128 02 00000003 128 02 00000003 0 02 00000003 100 Upload Time 01 40 Image Size 16777217 bytes Component requires Payload Cold Reset Performing activation stage Firmware upgrade ...

Page 289: ...c Sensors Sensor Number Sensor Name Sensor Type Event Reading Type Event Data Byte 1 Event Data Byte 2 Event Data Byte 3 Event Threshold Description Assertion Deassertion Rearm 0 Hot Swap Carrier Hot Swap 0xF0 Sensor specific discrete 0x6F 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 7 4 Cause 3 0 Previous State FRU ID 0x0 M0 0x1 M1 0x2 M2 0x3 M3 0x4 M4 0x5 M5 0x6 M6 0x7 M7 Asrt Auto 1 Hot Swap RTM Hot Swap 0x...

Page 290: ...rved reading 0x0 IPMB A disabled IPMB B disabled 0x1 IPMB A enabled IPMB B disabled 0x2 IPMB A disabled IPMB B enabled 0x3 IPMB A enabled IPMB B enabled Asrt Auto Table 9 2 ATCA 7540 Specific Sensors continued Sensor Number Sensor Name Sensor Type Event Reading Type Event Data Byte 1 Event Data Byte 2 Event Data Byte 3 Event Threshold Description Assertion Deassertion Rearm ...

Page 291: ...nvalid F W software 0x6 Hardware Change successful 0x7 Software or F W change successful Asrt Auto 4 Mid air temp Temp 0x01 Threshold 0x01 reading threshold unr uc unc Asrt Deass Auto 5 3 3 V MGMT Voltage 0x02 Threshold 0x01 reading threshold unr uc lnr lc Asrt Deass Auto 6 12 V Voltage 0x02 Threshold 0x01 reading threshold unr uc lnr lc Asrt Deass Auto Table 9 2 ATCA 7540 Specific Sensors continu...

Page 292: ... uc unc Asrt Deass Auto 12 BMC Watchdog Watchdog 2 0x23 Sensor specific discrete 0x6F 0x0 0x1 0x2 0x3 0x8 See IPMI Spec 0xFF 0x0 Timer expired 0x1 Hard Reset 0x2 Power Down 0x3 Power Cycle 0x8 Timer Interrupt Asrt Auto 13 Fw Progress System Firmware Progress 0x0F Sensor specific discrete 0x6F 0x0 0x1 0x2 See IPMI Spec See Table BIOS Supported IPMI Events on page 214 0x0 System Firmware Error 0x1 S...

Page 293: ...6 boot completed Asrt Auto 15 Boot Error Boot Error 0x1E Sensor specific discrete 0x6F 0x0 0xFF 0xFF 0x0 No Bootable media Asrt Auto 16 Boot Initiated System Boot Initiated 0x1D Sensor specific discrete 0x6F 0x0 0x1 0xFF 0xFF 0x0 Initiated by power up 0x1 Initiated by hard reset Asrt Auto Table 9 2 ATCA 7540 Specific Sensors continued Sensor Number Sensor Name Sensor Type Event Reading Type Event ...

Page 294: ... Auto 18 Critical IRQ Critical Interrupt 0x13 Sensor specific discrete 0x6F 0x4 0x5 Bus Number See Table BIOS Supported IPMI Events on page 214 Function Device See Table BIOS Supported IPMI Events on page 214 0x4 PCI PERR 0x5 PCI SERR Asrt Auto 19 Battery Battery 0x29 Sensor specific discrete 0x6F 0x1 0xFF 0xFF 0x1 Battery failed Asrt Auto Table 9 2 ATCA 7540 Specific Sensors continued Sensor Numb...

Page 295: ...See IPMI Spec 0xFF 0x0 Presence detected 0x1 Power Supply Failure detected Asrt Auto 23 48 V A Volts Voltage 0x02 Threshold 0x01 reading threshold unr uc lnr lc Asrt Deass Auto 24 48 V B Volts Voltage 0x02 Threshold 0x01 reading threshold unr uc lnr lc Asrt Deass Auto 25 48 V Amps Current 0x03 Threshold 0x01 reading threshold No Thresholds Auto 26 HoldUp Cap Volts Voltage 0x02 Threshold 0x01 readi...

Page 296: ...PMI Spec 0xFF 0x0 Presence detected 0x1 Power Supply Failure detected Asrt Deass Auto 30 48 V B Supply Power Supply 0x08 Sensor specific discrete 0x6F 0x0 0x1 See IPMI Spec 0xFF 0x0 Presence detected 0x1 Power Supply Failure detected Asrt Deass Auto 31 BIOS POST code OEM 0xD1 Sensor specific discrete 0x6F 0x0 0x0 No events for this sensor Readingaccording to EFI BIOS port80 status codes Asrt Auto ...

Page 297: ...CPI State System ACPI Power State 0x22 Sensor specific discrete 0x6F 0x0 0x3 0x5 0xFF 0xFF 0x0 S0 0x3 S3 0x5 S5 Asrt Auto 34 CPU Status Processor 0x07 Sensor specific discrete 0x6F 0x0 0x1 0xFF 0xFF 0x0 IERR 0x1 Thermal Trip Asrt Auto 35 ME Pwr Fail OEM 0xE0 Sensor specific discrete 0x6F 0x0 0x1 0x2 0x7 0xFF 0xFF 0x0 Me Fail State 0x1 Me Fail State 0x2 Me Fail State Asrt Auto Table 9 2 ATCA 7540 S...

Page 298: ...G 0x1 5V AUX PG 0x2 5V PG 0x7 1 5V PG Asrt Auto 39 PYLD Pwr Fail C3 OEM 0xE4 Sensor specific discrete 0x6F 0x0 0x1 0x2 0x7 0xFF 0xFF 0x0 VPP CPU0 PG 0x1 VPP CPU1 PG 0x2 VDD CPU0 PG 0x7 VCCIN CPU1 PG Asrt Auto 40 CPU0 temp Temp 0x01 Threshold 0x01 reading threshold unr uc unc Asrt Deass Auto 41 CPU1 temp Temp 0x01 Threshold 0x01 reading threshold unr uc unc Asrt Deass Auto 42 CPU0 DDR0 Temp Temp 0x...

Page 299: ...Temp 0x01 Threshold 0x01 reading threshold unr uc unc Asrt Deass Auto 48 CPU1 DDR0 Temp Temp 0x01 Threshold 0x01 reading threshold unr uc unc Asrt Deass Auto 49 CPU1 DDR1 Temp Temp 0x01 Threshold 0x01 reading threshold unr uc unc Asrt Deass Auto 50 CPU1 DDR2 Temp Temp 0x01 Threshold 0x01 reading threshold unr uc unc Asrt Deass Auto 51 CPU1 DDR3 Temp Temp 0x01 Threshold 0x01 reading threshold unr u...

Page 300: ... threshold unr uc unc Asrt Deass Auto 56 XL710 Temp Temp 0x01 Threshold 0x01 reading threshold unr uc unc Asrt Deass Auto 57 IPMC POST Management Subsystem Health 0x28 Digital Discrete 0x06 0x0 0x1 0xFF 0xFF 0x0 Performance Met 0x1 Performance Lags Asrt Auto 58 ap force alm OEM 0xDB Sensor specific Discrete 0x6F 0x0 Cause MSB AP Force ALM Cause Asrt Auto Table 9 2 ATCA 7540 Specific Sensors contin...

Page 301: ...re via IPMI event messages Figure 9 3 Location of Temperature Sensors P31 P30 P23 P20 P32 P10 P333 ZONE 1 ZONE 2 ZONE 3 ZONE 2 DIMM A Temp Sensor 42 DIMM B Temp Sensor 43 DIMM C Temp Sensor 44 DIMM D Temp Sensor 45 DIMM E Temp Sensor 46 DIMM F Temp Sensor 47 CPU0 Temp Sensor 40 MID Temp Sensor 4 CPU1 Temp Sensor 41 Outlet Temp Sensor 11 PCH Temp Sensor 54 Fortville XL710 Sensor 56 Board Temp Senso...

Page 302: ...or implemented with sensor type 0x29 Battery is used to inform the IPMC about low failed RTC The Critical IRQ sensor implemented with sensor type 0x13 Critical Interrupt is used to give PCI errors and NMIs The boot error sensor implemented with sensor type 0x1E Boot Error is used to pass boot failure information to the IPMC In all cases above the IPMC sends an event to the ShMM 9 4 2 Boot Bank Sup...

Page 303: ...is automatic shutdown is meant to keep the IPMC s state in line with the payload state 9 4 5 Power Interface Sensors An Ericsson power input module PIM4328 is used for the 48 V to 12 V conversion monitoring The PIM includes sensors which monitor the shelf s 48 V input feed current hold up capacitor voltage on board temperature and internal status The status sensor reading can be decoded as shown i...

Page 304: ... B is Enabled Bit 0 Voltage Feed A Enabled 0 Enable A is Disabled 1 Enable A is Enabled Table 9 4 Status Sensor s Sensor Reading continued Table 9 5 Voltage and Temperature Sensor Devices I C Address I C bus Domain Sensor Name Purpose refertoFigure9 3 Location of Temperature Sensors on page 301 Device 0x50 IPMC private 2 Front blade 48 V A Volts 48 V B Volts 48 V Amps Holdup Cap Volts PWR Entry Te...

Page 305: ...mp DIMM F Temp DIMM G Temp DIMM H Temp DIMM J Temp DIMM K Temp DIMM L Temp DIMM M Temp PCH Temp ME Engine Internal ADC Front blade Mid air temp 3 3 V MGMT 12 V 5 V RTM 3 3 V MGMT RTM 12 V MID Temp Management Power Voltage 12 V Power Voltage 5 V Power Voltage RTM Management Power Voltage RTM 12 V Power Voltage A2F ADC 0x98 IPMC private Front blade Board Temp XL710 Temp Board Temp Fortville XL710 Te...

Page 306: ...switch SW 100 1 from ON to OFF IPMC Controlled Powering The IPMC shutting down the payload power signal IPMC_VP48_EN_ is deserted For more information see Table 5 47 See Table 5 48 for all possible failing states and their coding When the blade is powered via switch SW100 1 the debug mode is enabled where some timeouts are disabled 9 4 10 Payload Power Failure Cause Sensor The IPMC uses three sens...

Page 307: ...ve and both IPMB busses IPMB A and IPMB B are enabled EEPROM Verifies that the EEPROM contents are readable via I C Since the IPMC stores its runtime and persistent data here proper operation is crucial Master Only I C Verifies that all expected devices attached to the master only I C bus are accessible To obtain results of POST the IPMC supports the IPMI standard command Get Self Test Results wit...

Page 308: ...age 308 9 7 1 MAC Address FRU OEM Records The Artesyn Embedded Technologies MAC Address record is specified in the following table Table 9 6 FRU Information and SEL at EEPROM Storage I C Address I C bus Domain Purpose 0xA0 IPMC Front blade SEL 0xA2 IPMC Front blade FRU Information and Bios Boot Parameter Device internal MMC RTM FRU Information Table 9 7 Artesyn MAC Address Record Offset Length Des...

Page 309: ...set Length Description 0 1 Interface Type Refer to XTable 8 Interface Type Assignments 1 1 Length Identifier for example 6 48 bit MAC 8 WWPN 2 1 MAC Address Count M specifying a continuous poolof MAC addresses starting with the MAC address specified in this descriptor M 1 this descriptor specifies one MAC address M 1 this descriptor specifies a pool of MAC addresses with M count 3 6 MAC Address Ca...

Page 310: ... ATCA 7540 blade provides the following FRU instances FRU 0 front blade management and switch FRU 1 RTM Each FRU instance can be reset separately 05h Serial over LAN SOL 06h Fibre Channel WWPN 07h AMC MicroTCA Common Options Region 08h AMC MicroTCA Fat Pipe Region 09h AMC MicroTCA Extended Fat Pipe Region 10h ATCA Update Channel 11h Multi type Base Fabric and Update channel or two types of it are ...

Page 311: ...saved back into the non volatile memory of the IPMC The IPMI command being used to manage the boot configuration variables is called Set Get System Boot Options together with parameter 100 For details see System Boot Options Commands on page 233 Table 9 10 Power Consumption Depending on the Product Version Item Value Description Dynamic power reconfiguration support No While the blade is powered i...

Page 312: ... chunks of 16 bytes at a time For this reason the IPMC memory is divided into numbered blocks of 16 bytes which need to be addressed individually For this purpose the block selector field in the request data field is used Table 9 11 IPMC Boot Parameter Storage Format Byte Description 0 1 Number of bytes used for boot parameters LSB first The number of bytes must be calculated and written into thes...

Page 313: ...es a serial connector at the front The IPMC provides an OEM command called Set Get Serial Output to be used to influence this serial interface routing default The serial line selection is implemented non persistently to ensure that the serial interfaces can be accessed easily after power up 9 13 BIOS Boot Bank Selection The ATCA 7540 provides redundant payload boot flashes for manual and automatic...

Page 314: ...ot banks and to reset the processor in case the boot firmware hangs accidentally Fail safe logic can be enabled or disabled at any time with IPMI OEM command called Set Get Feature Configuration and parameter 224 For details see Set Feature Configuration on page 255 BIOS Setup Menu Typically fail safe logic is used to protect a BIOS firmware upgrade to recover even when the boot image programmed d...

Page 315: ...event is logged as follows Sensor Type 0x0F System Firmware Progress Event Reading Type Code 0x6F Sensor Specific Event Data Byte 1 0xA1 System Firmware Hang Event Data Byte 2 0x00 CPU instance Event Data Byte 3 0xXX Failed Boot Bank ID 0 Bank A 1 Bank B Figure 9 4 Fail Safe Logic Diagram Swap Boot Bank and send a System Firmware Hang event to the ShMM Start Send a BMC W atchdog event to the ShMM ...

Page 316: ...ces can be reversed by the IPMC for this to work the IPMC has to drive the chip select signals to the SPI flashes The final decision about which of the two devices is active and standby is made by the IPMC The IPMC needs to control the Glue Logic FPGA during power up The FPGA Bank selection is implemented such that swapping the SPI flashes is in effect Swapping FPGA banks is only possible with the...

Page 317: ...FPGA firmware hangs accidentally Fail protect can be enabled or disabled at any time using an IPMI OEM command called Set Get Feature Configuration and parameter 224 For details see Set Feature Configuration on page 255 or BIOS setup menu During initial power on the IPMC selects the FPGA bank stored in NVRAM and evaluates the FPGA DONE signal If the provided signal is not asserted the IPMC selects...

Page 318: ...mer expired Failed once start Deassert signal FPGA_PROGRAM Evaluate signal FPGA Done Yes Yes Yes Both FPGA banks corrupted Crisis Recovery FPGA Load Done Swap Boot Bank to protect working image Remote Crisis Recovery Mode M1 Success Select Boot Bank from NVRAM Set Timer send a System Firmware Hang event to the ShMM Set failprotect to FAILED_ONCE Set failprotect to FAILED_TWICE ...

Page 319: ...rotect logic is activated 9 14 3 Remote Crisis Recover Mode This mode is entered when both FPGA flashes are corrupted and the FPGA cannot be loaded The IPMC moves into hot swap state M1 and waits for subsequent firmware upgrades initiated from the ShMM 9 15 Settable Graceful Shutdown Timeout The IPMI command Set Get System Boot Options together with the OEM parameter 98 can be used to specify the ...

Page 320: ...L a software emulated RTC is enabled which upon startup requests the local time from the shelf manager by sending an IPMI standard command Get SEL Time Once the initial time is received the IPMC maintains the time locally and no further synchronization is performed with the shelf manager ...

Page 321: ...fer to the following table for related specifications As an additional help a source for the listed document is provided Please note that while these sources have been verified the information is subject to change without notice Table A 1 Artesyn Embedded Technologies Publications Document Title Publication Number ATCA 7540 Quick Start Guide 6806871A02 ATCA 7540 Safety Notes Summary 6806871A03 Bas...

Page 322: ...Related Documentation 322 ATCA 7540 Installation and Use 6806871A01A ...

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Page 324: ...esyn and the Artesyn Embedded Technologies logo are trademarks and service marks of Artesyn Embedded Technologies Inc All other product or service names are the property of their respective owners 2018 Artesyn Embedded Technologies Inc ...

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