Artesyn Embedded Technology ATCA-7540, Installation And Use Manual, Page: 120 / 324

Maps and Registers
120 ATCA-7540 Installation and Use (6806871A01A )
1
Overrun error (OE) indicator
When OE is set, it indicates that before the character in the
RBR was read, it was overwritten by the next character
transferred into the register. OE is cleared every time the
CPU reads the contents of the LSR. If the FIFO mode data
continues to fill the FIFO beyond the trigger level, an overrun
error occurs only after the FIFO is full and the next character
has been completely received in the shift register. An
overrun error is indicated to the CPU as soon as it happens.
The character in the shift register is overwritten but it is not
transferred to the FIFO:
1: Overrun error occurred
0: No overrun error
0 LPC: r
2
Parity Error (PE) indicator
When PE is set, it indicates that the parity of the received
data character does not match the parity selected in the LCR
(bit 4). PE is cleared every time the CPU reads the contents of
the LSR. In the FIFO mode, this error is associated with the
particular character in the FIFO to which it applies. This error
is revealed to the CPU when its associated character is at the
top of the FIFO:
1: Parity error occurred
0: No parity error
0 LPC: r
3
Framing Error (FE) indicator
When FE is set, it indicates that the received character did
not have a valid (set) stop bit. FE is cleared every time the
CPU reads the contents of the LSR. In the FIFO mode, this
error is associated with the particular character in the FIFO to
which it applies. This error is revealed to the CPU when its
associated character is at the top of the FIFO. The ACE tries to
resynchronize after a framing error. To accomplish this, it is
assumed that the framing error is due to the next start bit.
The ACE samples this start bit twice and then accepts the
input data:
1: Framing error occurred
0: No framing error
0 LPC: r
Table 5-33. Line Status Register (LSR) (continued)
LPC I/O Address: Base + 5
Bit Description Default Access