Artesyn Embedded Technology ATCA-7540, Installation And Use Manual, Page: 103 / 324

Maps and Registers
ATCA-7540 Installation and Use (6806871A01A) 103
5.1.1.2 I²C Register Decoding
All I²C accesses from the IPMC towards the FPGA when the I²C master uses the I²C slave address
0x7F (the corresponding 8-bit slave address is 0xFE).
5.1.2 POST Code Register
The FPGA provides an 8-bit register to store POST codes to the LPC I/O address 0x80. The 8-bit
register data is displayed as two hex values by two 7-segment
LED displays.
The IPMC can read the POST code using the SPI interface (with the signal IPMC_SPI_SS_FPGA_
asserted) and the SPI address 0x7F.
The two 7-segment LED displays are also used for power failure indication.
5.1.3 Super IO Configuration Register
After an LPC Reset (PCH_PLTRST_ is asserted) or “Power On Reset” the Super IO is in the Run
Mode with the UARTs disabled. They may be configured using the LPC I/O Address Range
(INDEX and DATA) by placing the Super IO into Configuration Mode.
Table 5-4. IPMC SPI Register
I²C Address Range Address Range Name Description
0x00 - 0x7F IPMC_REGISTERS
All FPGA registers which are
accessible from IPMC
Table 5-5. POST Code Register
LPC I/O Address: 0x80
IPMC I²C Address: 0x7f
Bit Description Default Access
7:0 POST codes from host 0
LPC: r/w
IPMC: r